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DS077 Datasheet, PDF (69/108 Pages) Xilinx, Inc – Product Availability
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Spartan-IIE FPGA Family: Pinout Tables
FT256 Pinouts (XC2S50E, XC2S100E,
XC2S150E, XC2S200E, XC2S300E, XC2S400E)
(Continued)
Pad Name
Function Bank Pin
LVDS
Async.
Output
Option
VREF
Option
I/O (D5),
3 L13
All
-
L35N_YY
I/O, L35P_YY 3 K14
All
-
I/O, L34N
3 K15 XC2S100E,
-
150E, 400E
I/O, L34P
3 K16 XC2S100E,
-
150E, 400E
I/O, L33N
3 L12 XC2S50E,
-
100E, 150E,
200E,
300E(1)
I/O, L33P
3 K12 XC2S50E,
-
100E, 150E,
200E,
300E(1)
I/O, VREF
3 K13 XC2S50E,
All
Bank 3, L32N
300E, 400E
I/O (D4), L32P 3 J14 XC2S50E,
-
300E, 400E
I/O, L31N
3 J15 XC2S100E,
-
150E, 200E,
400E
I/O, L31P
3 J16 XC2S100E, XC2S400E
150E, 200E,
400E
I/O (TRDY)
3 J13
-
-
I/O (IRDY),
2
L30N_YY
I/O, L30P_YY 2
I/O, L29N
2
I/O, L29P
2
I/O (D3), L28N 2
H16
All
-
G16
All
-
H14 XC2S100E, XC2S400E
150E, 200E,
400E
H15 XC2S100E,
-
150E, 200E,
400E
G15 XC2S50E,
-
300E, 400E
FT256 Pinouts (XC2S50E, XC2S100E,
XC2S150E, XC2S200E, XC2S300E, XC2S400E)
(Continued)
Pad Name
Function Bank Pin
LVDS
Async.
Output
Option
VREF
Option
I/O, VREF
2 F16 XC2S50E,
All
Bank 2, L28P
300E, 400E
I/O, L27N
2 H13 XC2S50E,
-
100E, 150E,
200E,
300E(1)
I/O, L27P
2 G14 XC2S50E,
-
100E, 150E,
200E,
300E(2)
I/O, L26N
2 F15 XC2S100E,
-
150E, 400E
I/O, L26P
2 E16 XC2S100E,
-
150E, 400E
I/O, L25N_YY 2 G13
All
-
I/O (D2),
2 F14
All
-
L25P_YY
I/O (D1), L24N 2 E15 XC2S50E,
-
300E, 400E
I/O, L24P
2 D16 XC2S50E, XC2S100E,
300E, 400E 150E, 200E,
300E, 400E
I/O, L23N
2 F13 XC2S150E,
-
200E, 400E
I/O, L23P
2 E14 XC2S150E,
-
200E, 400E
I/O, L22N
2 D15 XC2S50E,
-
150E, 200E,
300E, 400E
I/O, VREF
2 C16 XC2S50E,
All
Bank 2, L22P
150E, 200E,
300E, 400E
I/O, L21N
2 G12 XC2S50E,
-
100E, 200E,
300E
I/O, L21P
2 F12 XC2S50E,
-
100E, 200E,
300E
I/O, L20N
2 E13 XC2S100E,
-
200E, 300E
DS077-4 (2.3) June 18, 2008
www.xilinx.com
69
Product Specification
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