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DS077 Datasheet, PDF (65/108 Pages) Xilinx, Inc – Product Availability
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Spartan-IIE FPGA Family: Pinout Tables
PQ208 Pinouts (XC2S50E, XC2S100E,
XC2S150E, XC2S200E, XC2S300E)
Pad Name
Function Bank Pin
LVDS
Async.
Output
Option
VREF
Option
I/O, VREF
1 P178 XC2S50E,
All
Bank 1, L6P
200E, 300E
I/O, L6N
1 P179 XC2S50E,
-
200E, 300E
I/O
1 P180
-
-
I/O (DLL),
1 P181
-
-
L5P
GCK2, I
1 P182
-
-
GND
- P183
-
-
VCCO
- P184
-
-
GCK3, I
0 P185
-
-
VCCINT
- P186
-
-
I/O (DLL),
0 P187
-
-
L5N
I/O, L4P
0 P188 XC2S50E,
-
200E, 300E
I/O, VREF
0 P189 XC2S50E,
All
Bank 0, L4N
200E, 300E
GND
- P190
-
-
I/O, L3P
0 P191 XC2S50E,
-
200E, 300E
I/O, L3N
0 P192 XC2S50E,
-
200E, 300E
I/O, L2P
0 P193 XC2S50E,
-
100E, 200E,
300E
I/O, L2N
0 P194 XC2S50E,
-
100E, 200E,
300E
VCCINT
- P195
-
-
VCCO
- P196
-
-
GND
- P197
-
-
I/O, L1P
0 P198 XC2S50E,
-
100E, 200E,
300E
I/O, L1N
0 P199 XC2S50E, XC2S100E,
100E, 200E, 150E, 200E,
300E
300E
I/O
0 P200
-
-
PQ208 Pinouts (XC2S50E, XC2S100E,
XC2S150E, XC2S200E, XC2S300E)
Pad Name
Function Bank Pin
LVDS
Async.
Output
Option
VREF
Option
I/O
0 P201
-
-
I/O,
0 P202
All
-
L0P_YY
I/O, VREF
0 P203
All
All
Bank 0,
L0N_YY
I/O
0 P204
-
-
I/O
0 P205
-
XC2S200E,
300E
I/O
0 P206
-
-
TCK
- P207
-
-
VCCO
- P208
-
-
PQ208 Differential Clock Pins
P
Clock Bank Pin Name Pin
GCK0 4 P80 GCK0, I P81
GCK1 5 P77 GCK1, I P75
GCK2 1 P182 GCK2, I P181
GCK3 0 P185 GCK3, I P187
N
Name
I/O (DLL),
L31P
I/O (DLL),
L31N
I/O (DLL),
L5P
I/O (DLL),
L5N
DS077-4 (2.3) June 18, 2008
www.xilinx.com
65
Product Specification
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