DS077 Datasheet, PDF (36/108 Pages) Xilinx, Inc – Product Availability

Spartan-IIE FPGA Family: DC and Switching Characteristics
R
Global Clock Setup and Hold for LVTTL Standard, with DLL (Pin-to-Pin)
Symbol
T_PSDLL / T_PHDLL
Description
Input setup and hold time relative to global clock input signal
for LVTTL standard, no delay, IFF,⁽¹⁾ with DLL
Speed Grade
-7
-6
Min
Min
1.6 / 0
1.7 / 0
Units
ns
Notes:
1. IFF = Input Flip-Flop or Latch
2. Setup time is measured relative to the Global Clock input signal with the fastest route and the lightest load. Hold time is measured
relative to the Global Clock input signal with the slowest route and heaviest load.
3. DLL output jitter is already included in the timing calculation.
4. For data input with different standards, adjust the setup time delay by the values shown in IOB Input Delay Adjustments for Different
Standards, page 38. For a global clock input with standards other than LVTTL, adjust delays with values from the I/O Standard
Global Clock Input Adjustments, page 42.
5. A zero hold time listing indicates no hold time or a negative hold time.
Global Clock Setup and Hold for LVTTL Standard, without DLL (Pin-to-Pin)
Speed Grade
-7
-6
Symbol
T_PSFD / T_PHFD
Description
Input setup and hold time relative
to global clock input signal for
LVTTL standard, with delay, IFF,⁽¹⁾
without DLL
Device
XC2S50E
XC2S100E
XC2S150E
XC2S200E
XC2S300E
XC2S400E
XC2S600E
Min
1.8 / 0
1.8 / 0
1.9 / 0
1.9 / 0
2.0 / 0
2.0 / 0
2.1 / 0
Min
1.8 / 0
1.8 / 0
1.9 / 0
1.9 / 0
2.0 / 0
2.0 / 0
2.1 / 0
Units
ns
ns
ns
ns
ns
ns
ns
Notes:
1. IFF = Input Flip-Flop or Latch
2. Setup time is measured relative to the Global Clock input signal with the fastest route and the lightest load. Hold time is measured
relative to the Global Clock input signal with the slowest route and heaviest load.
3. For data input with different standards, adjust the setup time delay by the values shown in IOB Input Delay Adjustments for Different
Standards, page 38. For a global clock input with standards other than LVTTL, adjust delays with values from the I/O Standard
Global Clock Input Adjustments, page 42.
36
www.xilinx.com
DS077-3 (v2.3) June 18, 2008
Product Specification