DS077 Datasheet, PDF (45/108 Pages) Xilinx, Inc – Product Availability

R
Spartan-IIE FPGA Family: DC and Switching Characteristics
CLB Switching Characteristics
Delays originating at F/G inputs vary slightly according to the input used. The values listed below are worst-case. Precise
values are provided by the timing analyzer.
Symbol
Description
Combinatorial Delays
T_ILO
T_IF5
T_IF5X
T_IF6Y
T_F5INY
T_IFNCTL
4-input function: F/G inputs to X/Y outputs
5-input function: F/G inputs to F5 output
5-input function: F/G inputs to X output
6-input function: F/G inputs to Y output via F6 MUX
6-input function: F5IN input to Y output
Incremental delay routing through transparent latch to
XQ/YQ outputs
T_BYYB
BY input to YB output
Sequential Delays
T_CKO
FF clock CLK to XQ/YQ outputs
T_CKLO
Latch clock CLK to XQ/YQ outputs
Setup/Hold Times with Respect to Clock CLK
T_ICK / T_CKI 4-input function: F/G inputs
T_IF5CK / T_CKIF5 5-input function: F/G inputs
T_F5INCK / T_CKF5IN 6-input function: F5IN input
T_IF6CK / T_CKIF6 6-input function: F/G inputs via F6 MUX
T_DICK / T_CKDI BX/BY inputs
T_CECK / T_CKCE CE input
T_RCK / T_CKR SR/BY inputs (synchronous)
Clock CLK
T_CH
T_CL
Set/Reset
Pulse width, High
Pulse width, Low
T_RPW
T_RQ
Pulse width, SR/BY inputs
Delay from SR/BY inputs to XQ/YQ outputs
(asynchronous)
F_TOG
Toggle frequency (for export control)
Speed Grade
-7
-6
Min Max Min Max
Units
0.18 0.42 0.18 0.47 ns
0.3 0.8 0.3 0.9 ns
0.3 0.8 0.3 0.9 ns
0.3 0.9 0.3 1.0 ns
0.04 0.2 0.04 0.22 ns
-
0.7
-
0.8 ns
0.18 0.46 0.18 0.51 ns
0.3 0.9 0.3 1.0 ns
0.3 0.9 0.3 1.0 ns
1.0 / 0 - 1.1 / 0 -
ns
1.4 / 0 - 1.5 / 0 -
ns
0.8 / 0 - 0.8 / 0 -
ns
1.5 / 0 - 1.6 / 0 -
ns
0.7 / 0 - 0.8 / 0 -
ns
0.7 / 0 - 0.7 / 0 -
ns
0.52 / 0 - 0.6 / 0 -
ns
1.3
-
1.4
-
ns
1.3
-
1.4
-
ns
2.1
-
2.4
-
ns
0.3 0.9 0.3 1.0 ns
-
400
-
357 MHz
DS077-3 (v2.3) June 18, 2008
www.xilinx.com
45
Product Specification