DS077 Datasheet, PDF (104/108 Pages) Xilinx, Inc – Product Availability

Spartan-IIE FPGA Family: Pinout Tables
R
FG676 Pinouts (XC2S400E, XC2S600E) (Continued)
Pad Name
Function
Bank Pin
LVDS Async.
Output Option
VREF
Option
I/O, VREF Bank 1,
1 D14
XC2S600E
All
L25P
I/O, L25N
1 C14
XC2S600E
-
I/O
1 J13
-
-
I/O, L24P
1 C13
-
-
I/O, L24N
1 D13
-
-
I/O
1 H13
-
-
I/O (DLL), L23P
1 B14
-
-
GCK2, I
1 A14
-
-
Device-Specific Pinouts
XC2S400E
XC2S600E
I/O, VREF Bank 1,
L25P
I/O, VREF Bank 1,
L25P_Y
I/O, L25N
I/O, L25N_Y
-
I/O
I/O, L24P
I/O, L24P
I/O, L24N
I/O, L24N
-
I/O
I/O (DLL), L23P
I/O (DLL), L23P
GCK2, I
GCK2, I
GCK3, I
I/O (DLL), L23N
I/O
I/O, L22P_YY
I/O, L22N_YY
I/O, L21P
I/O, VREF Bank 0,
L21N
I/O, L20P
I/O, L20N
I/O
I/O, L19P_YY
I/O, L19N_YY
I/O
I/O, L18P_YY
I/O, VREF Bank 0,
L18N_YY
I/O, L17P_YY
I/O, L17N_YY
I/O
I/O, L16P
I/O, L16N
I/O
I/O, L15P_YY
I/O, L15N_YY
I/O, L14P_YY
0 A13
0 B13
0 E13
0 F13
0 G13
0 A12
0 B12
0 D12
0 E12
0 F12
0 G12
0 H12
0 J12
0 A11
0 B11
0 E11
0 F11
0 C11
0 G11
0 H11
0 C10
0 A10
0 B10
0 D10
-
-
-
All
All
XC2S600E
XC2S600E
XC2S600E
XC2S600E
-
All
All
-
All
All
All
All
-
-
-
-
All
All
All
-
GCK3, I
GCK3, I
-
I/O (DLL), L23N
I/O (DLL), L23N
-
-
I/O
-
I/O, L22P_YY
I/O, L22P_YY
-
I/O, L22N_YY
I/O, L22N_YY
-
-
I/O, L21P_Y
All
I/O, VREF Bank 0
I/O, VREF Bank 0,
L21N_Y
-
I/O, L20P
I/O, L20P_Y
-
I/O, L20N
I/O, L20N_Y
-
-
I/O
-
I/O, L19P_YY
I/O, L19P_YY
-
I/O, L19N_YY
I/O, L19N_YY
-
-
I/O
-
I/O, L18P_YY
I/O, L18P_YY
All
I/O, VREF Bank 0, I/O, VREF Bank 0,
L18N_YY
L18N_YY
-
I/O, L17P_YY
I/O, L17P_YY
-
I/O, L17N_YY
I/O, L17N_YY
-
-
I/O
-
I/O, L16P
I/O, L16P
-
I/O, L16N
I/O, L16N
-
-
I/O
-
I/O, L15P_YY
I/O, L15P_YY
-
I/O, L15N_YY
I/O, L15N_YY
-
I/O, L14P_YY
I/O, L14P_YY
104
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DS077-4 (2.3) June 18, 2008
Product Specification