DS077 Datasheet, PDF (44/108 Pages) Xilinx, Inc – Product Availability

Spartan-IIE FPGA Family: DC and Switching Characteristics
R
Period Tolerance: the allowed input clock period change in nanoseconds.
TCLKIN =
1
FCLKIN
TCLKIN +_ TIPTOL
Output Jitter: the difference between an ideal
reference clock edge and the actual design. Phase Offset and Maximum Phase Difference
Ideal Period
Actual Period
+/- Jitter
+ Maximum
Phase Difference
+ Phase Offset
Figure 22: Period Tolerance and Clock Jitter
DS001_52_090800
44
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DS077-3 (v2.3) June 18, 2008
Product Specification