DS077 Datasheet, PDF (38/108 Pages) Xilinx, Inc – Product Availability

Spartan-IIE FPGA Family: DC and Switching Characteristics
R
IOB Input Delay Adjustments for Different Standards
Input delays associated with the pad are specified for LVTTL. For other standards, adjust the delays by the values shown. A
delay adjusted in this way constitutes a worst-case limit.
Symbol
Description
Standard
Speed Grade
-7
-6
Units
Data Input Delay Adjustments
T_ILVTTL
T_ILVCMOS2
Standard-specific data input delay LVTTL
adjustments
LVCMOS2
0
0
ns
0
0
ns
T_ILVCMOS18
LVCMOS18
0.20
0.20
ns
T_ILVDS
LVDS
0.15
0.15
ns
T_ILVPECL
LVPECL
0.15
0.15
ns
T_{IPCI33_3}
PCI, 33 MHz, 3.3V
0.08
0.08
ns
T_{IPCI66_3}
PCI, 66 MHz, 3.3V
–0.11
–0.11
ns
T_IGTL
GTL
0.14
0.14
ns
T_IGTLP
GTL+
0.14
0.14
ns
T_IHSTL
HSTL
0.04
0.04
ns
T_ISSTL2
SSTL2
0.04
0.04
ns
T_ISSTL3
SSTL3
0.04
0.04
ns
T_ICTT
CTT
0.10
0.10
ns
T_IAGP
AGP
0.04
0.04
ns
38
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DS077-3 (v2.3) June 18, 2008
Product Specification