DS077 Datasheet, PDF (23/108 Pages) Xilinx, Inc – Product Availability

R
Configuration
at Power-up
V_CCO
No
AND
V_CCINT
High?
Yes
Configuration During
User Operation
User Pulls
PROGRAM
Low
FPGA
Drives INIT
and DONE Low
Clear
Configuration
Memory
Delay
Configuration
User Holding Yes
PROGRAM
Low?
No
User Holding ^Yes
INIT
Low?
No
FPGA
Samples
Mode Pins
Delay
Configuration
Load
Configuration
Data Frames
CRC
Correct?
No ^{FPGA Drives}
INIT Low
Abort Start-up
Yes
Start-up Sequence
FPGA Drives DONE High,
Activates I/Os,
Releases GSR net
User Operation
DS001_11_111501
Figure 16: Configuration Flow Diagram
Spartan-IIE FPGA Family: Functional Description
Clearing Configuration Memory
The device indicates that clearing the configuration memory
is in progress by driving INIT Low.
Delaying Configuration
At this time, the user can delay configuration by holding
either PROGRAM or INIT Low, which causes the device to
remain in the memory clearing phase. Note that the bidirec-
tional INIT line is driving a Low logic level during memory
clearing. Thus, to avoid contention, use an open-drain driver
to keep INIT Low.
With no delay in force, the device indicates that the memory
is completely clear by driving INIT High. The FPGA samples
its mode pins on this Low-to-High transition.
Loading Configuration Data
Once INIT is High, the user can begin loading configuration
data frames into the device. The details of loading the con-
figuration data are discussed in the sections treating the
configuration modes individually. The sequence of opera-
tions necessary to load configuration data using the serial
modes is shown in Figure 18. Loading data using the Slave
Parallel mode is shown in Figure 21, page 28.
CRC Error Checking
After the loading of configuration data, a CRC value embed-
ded in the configuration file is checked against a CRC value
calculated within the FPGA. If the CRC values do not
match, the FPGA drives INIT Low to indicate that an error
has occurred and configuration is aborted. Note that
attempting to load an incorrect bitstream causes configura-
tion to fail and can damage the device.
To reconfigure the device, the PROGRAM pin should be
asserted to reset the configuration logic. Recycling power
also resets the FPGA for configuration. See Clearing Con-
figuration Memory.
Start-up
The start-up sequence oversees the transition of the FPGA
from the configuration state to full user operation. A match
of CRC values, indicating a successful loading of the config-
uration data, initiates the sequence.
DS077-2 (v2.3) June 18, 2008
www.xilinx.com
23
Product Specification