DS077 Datasheet, PDF (47/108 Pages) Xilinx, Inc – Product Availability

R
Spartan-IIE FPGA Family: DC and Switching Characteristics
CLB Distributed RAM Switching Characteristics
Symbol
Description
Sequential Delays
T_SHCKO16 Clock CLK to X/Y outputs (WE active, 16 x 1 mode)
T_SHCKO32 Clock CLK to X/Y outputs (WE active, 32 x 1 mode)
Setup/Hold Times with Respect to Clock CLK
T_AS / T_AH
T_DS / T_DH
T_WS / T_WH
Clock CLK
F/G address inputs
BX/BY data inputs (DIN)
CE input (WS)
T_WPH
T_WPL
T_WC
Pulse width, High
Pulse width, Low
Clock period to meet address write cycle time
CLB Shift Register Switching Characteristics
Symbol
Description
Sequential Delays
T_REG
Clock CLK to X/Y outputs
Setup/Hold Times with Respect to Clock CLK
T_SHDICK
T_SHCECK
Clock CLK
BX/BY data inputs (DIN)
CE input (WS)
T_SRPH
T_SRPL
Pulse width, High
Pulse width, Low
Block RAM Switching Characteristics
Symbol
Description
Sequential Delays
T_BCKO
Clock CLK to DOUT output
Setup/Hold Times with Respect to Clock CLK
T_BACK / T_BCKA
T_BDCK/ T_BCKD
T_BECK/ T_BCKE
T_BRCK/ T_BCKR
T_BWCK/ T_BCKW
Clock CLK
ADDR inputs
DIN inputs
EN inputs
RST input
WEN input
T_BPWH
T_BPWL
T_BCCS
Pulse width, High
Pulse width, Low
CLKA -> CLKB setup time for different ports
Speed Grade
-7
-6
Min
Max
Min Max
Units
0.6
1.5
0.6
1.7
ns
0.8
1.9
0.8
2.1
ns
0.42 / 0
-
0.5 / 0
-
ns
0.53 / 0
-
0.6 / 0
-
ns
0.7 / 0
-
0.8 / 0
-
ns
2.1
-
2.4
-
ns
2.1
-
2.4
-
ns
4.2
-
4.8
-
ns
Speed Grade
-7
-6
Min Max Min Max
Units
1.2
2.9
1.2
3.2
ns
0.53 / 0 -
0.6 / 0
-
ns
0.7 / 0
-
0.8 / 0
-
ns
2.1
-
2.4
-
ns
2.1
-
2.4
-
ns
Speed Grade
-7
-6
Min
Max
Min
Max
Units
0.6
3.1
0.6
3.5
ns
1.0 / 0
-
1.1 / 0
-
ns
1.0 / 0
-
1.1 / 0
-
ns
2.2 / 0
-
2.5 / 0
-
ns
2.1 / 0
-
2.3 / 0
-
ns
2.0 / 0
-
2.2 / 0
-
ns
1.4
-
1.5
-
ns
1.4
-
1.5
-
ns
2.7
-
3.0
-
ns
DS077-3 (v2.3) June 18, 2008
www.xilinx.com
47
Product Specification