DS077 Datasheet, PDF (15/108 Pages) Xilinx, Inc – Product Availability

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Spartan-IIE FPGA Family: Functional Description
CLB
Slice
LUT
MUXF6
LUT
Slice
MUXF5
LUT
LUT
MUXF5
DS077-2_05-111501
Figure 7: F5 and F6 Multiplexers
Each CLB has four direct feedthrough paths, one per LC.
These paths provide extra data input lines or additional local
routing that does not consume logic resources.
Arithmetic Logic
Dedicated carry logic provides capability for high-speed
arithmetic functions. The Spartan-IIE FPGA CLB supports
two separate carry chains, one per slice. The height of the
carry chains is two bits per CLB.
The arithmetic logic includes an XOR gate that allows a
1-bit full adder to be implemented within an LC. In addition,
a dedicated AND gate improves the efficiency of multiplier
implementations.
The dedicated carry path can also be used to cascade func-
tion generators for implementing wide logic functions.
BUFTs
Each Spartan-IIE FPGA CLB contains two 3-state drivers
(BUFTs) that can drive on-chip busses. The IOBs on the left
and right sides can also drive the on-chip busses. See Ded-
icated Routing, page 17. Each Spartan-IIE FPGA BUFT
has an independent 3-state control pin and an independent
input pin. The 3-state control pin is an active-Low enable
(T). When all BUFTs on a net are disabled, the net is High.
There is no need to instantiate a pull-up unless desired for
simulation purposes. Simultaneously driving BUFTs onto
the same net will not cause contention. If driven both High
and Low, the net will be Low.
Block RAM
Spartan-IIE FPGAs incorporate several large block RAM
memories. These complement the distributed RAM
Look-Up Tables (LUTs) that provide shallow memory struc-
tures implemented in CLBs.
Block RAM memory blocks are organized in columns. Most
Spartan-IIE devices contain two such columns, one along
each vertical edge. The XC2S400E has four block RAM col-
umns and the XC2S600E has six block RAM columns.
These columns extend the full height of the chip. Each
memory block is four CLBs high, and consequently, a
Spartan-IIE device 16 CLBs high will contain four memory
blocks per column, and a total of eight blocks.
Table 6: Spartan-IIE Block RAM Amounts
Spartan-IIE
Device
# of Blocks
Total Block RAM
Bits
XC2S50E
8
32K
XC2S100E
10
40K
XC2S150E
12
48K
XC2S200E
14
56K
XC2S300E
16
64K
XC2S400E
40
160K
XC2S600E
72
288K
Each block RAM cell, as illustrated in Figure 8, is a fully syn-
chronous dual-ported 4096-bit RAM with independent con-
trol signals for each port. The data widths of the two ports
can be configured independently, providing built-in
bus-width conversion.
RAMB4_S#_S#
WEA
ENA
RSTA
CLKA
ADD[#:0]
DIA[#:0]
DOA[#:0]
WEB
ENB
RSTB
CLKB
ADDRB[#:0]
DIB[#:0]
DOB[#:0]
DS001_05_060100
Figure 8: Dual-Port Block RAM
DS077-2 (v2.3) June 18, 2008
www.xilinx.com
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Product Specification