DS077 Datasheet, PDF (39/108 Pages) Xilinx, Inc – Product Availability

R
Spartan-IIE FPGA Family: DC and Switching Characteristics
IOB Output Switching Characteristics
Output delays terminating at a pad are specified for LVTTL with 12 mA drive and fast slew rate. For other standards, adjust
the delays with the values shown in IOB Output Delay Adjustments for Different Standards(1), page 40.
Speed Grade
-7
-6
Symbol
Description
Min Max Min Max
Propagation Delays
T_IOOP
O input to pad
1.0
2.7
1.0
2.9
T_IOOLP
O input to pad via transparent latch
1.2
3.1
1.2
3.4
3-state Delays
T_IOTHZ
T input to pad high impedance ⁽¹⁾
0.7
1.7
0.7
1.9
T_IOTON
T_IOTLPHZ
T input to valid data on pad
1.1
2.9
1.1
3.1
T input to pad high impedance via transparent latch⁽¹⁾ 0.8
2.0
0.8
2.2
T_IOTLPON
T_GTS
T input to valid data on pad via transparent latch
GTS to pad high impedance ⁽¹⁾
1.2
3.2
1.2
3.4
1.9
4.6
1.9
4.9
Sequential Delays
T_IOCKP
Clock CLK to pad
0.9
2.8
0.9
2.9
T_IOCKHZ
Clock CLK to pad high impedance (synchronous)⁽¹⁾ 0.7
2.0
0.7
2.2
T_IOCKON
Clock CLK to valid data on pad (synchronous)
1.1
3.2
1.1
3.4
Setup/Hold Times with Respect to Clock CLK
T_IOOCK / T_IOCKO O input
T_IOOCECK / T_IOCKOCE OCE input
T_IOSRCKO / T_IOCKOSR SR input (OFF)
T_IOTCK / T_IOCKT 3-state setup times, T input
T_IOTCECK / T_IOCKTCE 3-state setup times, TCE input
T_IOSRCKT / T_IOCKTSR 3-state setup times, SR input (TFF)
Set/Reset Delays
1.0 / 0 - 1.1 / 0 -
0.7 / 0 - 0.7 / 0 -
0.9 / 0 - 1.0 / 0 -
0.6 / 0 - 0.7 / 0 -
0.6 / 0 - 0.8 / 0 -
0.9 / 0 - 1.0 / 0 -
T_IOSRP
T_IOSRHZ
SR input to pad (asynchronous)
1.2
3.3
1.2
3.5
SR input to pad high impedance (asynchronous)⁽¹⁾
1.0
2.4
1.0
2.7
T_IOSRON
SR input to valid data on pad (asynchronous)
1.4
3.7
1.4
3.9
T_IOGSRQ
GSR to pad
3.8
8.5
3.8
9.7
Notes:
1. Three-state turn-off delays should not be adjusted.
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
DS077-3 (v2.3) June 18, 2008
www.xilinx.com
39
Product Specification