DS077 Datasheet, PDF(61/108 Page) Xilinx, Inc

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DS077 Datasheet, PDF (61/108 Pages) Xilinx, Inc – Product Availability

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Spartan-IIE FPGA Family: Pinout Tables

In the PQ208 package, all VCCO pins must be connected to

the same voltage.

PQ208 Pinouts (XC2S50E, XC2S100E,

XC2S150E, XC2S200E, XC2S300E)

Pad Name

Function Bank Pin

LVDS

Async.

Output

Option

VREF

Option

GND

TMS

I/O

XC2S200E,

300E

I/O

I/O, VREF

P6 XC2S50E,

All

Bank 7,

150E, 200E,

L49P

300E

I/O, L49N

P7 XC2S50E,

150E, 200E,

300E

I/O

I/O, L48P

7 P10 XC2S50E, XC2S100E,

300E 150E, 200E,

300E

I/O, L48N

7 P11 XC2S50E,

300E

GND

- P12

VCCO

- P13

VCCINT

- P14

I/O,

7 P15

All

L47P_YY

I/O,

7 P16

All

L47N_YY

I/O,

7 P17

All

L46P_YY

I/O,

7 P18

All

L46N_YY

GND

- P19

I/O, VREF

7 P20 XC2S50E,

All

Bank 7,

300E

L45P

I/O, L45N

7 P21 XC2S50E,

300E

PQ208 Pinouts (XC2S50E, XC2S100E,

XC2S150E, XC2S200E, XC2S300E)

Pad Name

Function Bank Pin

LVDS

Async.

Output

Option

VREF

Option

I/O

7 P22

I/O,

7 P23

All

L44P_YY

I/O (IRDY), 7 P24

All

L44N_YY

GND

- P25

VCCO

- P26

I/O (TRDY) 6 P27

VCCINT

- P28

I/O

6 P29

I/O, L43P

6 P30 XC2S50E,

300E

I/O, VREF

6 P31 XC2S50E,

All

Bank 6,

300E

L43N

GND

- P32

I/O,

6 P33

All

L42P_YY

I/O,

6 P34

All

L42N_YY

I/O,

6 P35

All

L41P_YY

I/O,

6 P36

All

L41N_YY

VCCINT

- P37

VCCO

- P38

GND

- P39

I/O, L40P

6 P40 XC2S50E,

300E

I/O, L40N

6 P41 XC2S50E, XC2S100E,

300E 150E, 200E,

300E

I/O

6 P42

I/O

6 P43

I/O

6 P44

DS077-4 (2.3) June 18, 2008

www.xilinx.com

Product Specification

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