DS077 Datasheet, PDF (42/108 Pages) Xilinx, Inc – Product Availability

Spartan-IIE FPGA Family: DC and Switching Characteristics
R
Clock Distribution Switching Characteristics
T_GPIO is specified for LVTTL levels. For other standards, adjust T_GPIO with the values shown in I/O Standard Global Clock
Input Adjustments.
Speed Grade
-7
-6
Symbol
Description
Max
Max
Units
GCLK IOB and Buffer
T_GPIO
T_GIO
Global clock pad to output
Global clock buffer I input to O output
0.7
0.7
ns
0.45
0.5
ns
I/O Standard Global Clock Input Adjustments
Delays associated with a global clock input pad are specified for LVTTL levels. For other standards, adjust the delays by the
values shown. A delay adjusted in this way constitutes a worst-case limit.
Symbol
Description
Standard
Speed Grade
-7
-6
Units
Data Input Delay Adjustments
T_GPLVTTL
T_GPLVCMOS2
Standard-specific global clock
input delay adjustments
LVTTL
LVCMOS2
0
0
ns
0
0
ns
T_GPLVCMOS18
LVCMOS18
0.2
0.2
ns
T_GPLVCDS
LVDS
0.38
0.38
ns
T_GPLVPECL
LVCPECL
0.38
0.38
ns
T_{GPPCI33_3}
PCI, 33 MHz, 3.3V
0.08
0.08
ns
T_{GPPCI66_3}
PCI, 66 MHz, 3.3V
–0.11
–0.11
ns
T_GPGTL
GTL
0.37
0.37
ns
T_GPGTLP
GTL+
0.37
0.37
ns
T_GPHSTL
HSTL
0.27
0.27
ns
T_GPSSTL2
SSTL2
0.27
0.27
ns
T_GPSSTL3
SSTL3
0.27
0.27
ns
T_GPCTT
CTT
0.33
0.33
ns
T_GPAGP
AGP
0.27
0.27
ns
Notes:
1. Input timing for GPLVTTL is measured at 1.4V. For other I/O standards, see the table Delay Measurement Methodology, page 41.
42
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DS077-3 (v2.3) June 18, 2008
Product Specification