DS077 Datasheet, PDF(71/108 Page) Xilinx, Inc

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DS077 Datasheet, PDF (71/108 Pages) Xilinx, Inc – Product Availability

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Spartan-IIE FPGA Family: Pinout Tables

FT256 Pinouts (XC2S50E, XC2S100E,

XC2S150E, XC2S200E, XC2S300E, XC2S400E)

(Continued)

Pad Name

Function Bank Pin

LVDS

Async.

Output

Option

VREF

Option

I/O, L6P

0 C7 XC2S50E,

200E, 300E,

400E

I/O, L6N

0 B7 XC2S50E,

200E, 300E,

400E

I/O

0 A6

I/O, L5P

0 B6 XC2S50E,

100E, 200E,

300E, 400E

I/O, L5N

0 C6 XC2S50E,

100E, 200E,

300E, 400E

I/O, L4P

0 A5 XC2S50E,

100E, 200E,

300E, 400E

I/O, L4N

0 B5 XC2S50E, XC2S100E,

100E, 200E, 150E, 200E,

300E, 400E 300E, 400E

I/O, L3P

0 D6 XC2S50E,

100E, 300E

I/O, L3N

0 E6 XC2S50E,

100E, 300E

I/O, L2P_YY

0 D5

All

I/O, VREF

0 C5

All

Bank 0,

L2N_YY

I/O, L1P_YY

0 B4

All

I/O, L1N_YY

0 C4

All

I/O, L0P_YY

0 A4

All

I/O, L0N_YY

0 A3

All

XC2S200E,

300E, 400E

I/O

0 B3

TCK

Notes:

1. Although designated with the _YY suffix in the XC2S50E,

XC2S100E, XC2S150E, XC2S200E, and XC2S300E, these

differential pairs are not asynchronous in the XC2S400E.

2. There is no pair L37.

FT256 Differential Clock Pins

Clock Bank Pin Name Pin

GCK0 4

T9 GCK0, I R9

GCK1 5

T8 GCK1, I R8

GCK2 1

B8 GCK2, I A8

GCK3 0

C8 GCK3, I D8

Additional FT256 Package Pins

VCCINT Pins

C14 D4

D13

E12

M5 M12

P14 -

VCCO Bank 0 Pins

F7 F8

VCCO Bank 1 Pins

F9 F10

VCCO Bank 2 Pins

G11

H11 H12

VCCO Bank 3 Pins

J11

J12 K11

VCCO Bank 4 Pins

L10 M9

Name

I/O (DLL),

L52P

I/O (DLL),

L52N

I/O (DLL),

L8P

I/O (DLL),

L8N

N13

DS077-4 (2.3) June 18, 2008

www.xilinx.com

Product Specification

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