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DS077 Datasheet, PDF (67/108 Pages) Xilinx, Inc – Product Availability
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Spartan-IIE FPGA Family: Pinout Tables
FT256 Pinouts (XC2S50E, XC2S100E,
XC2S150E, XC2S200E, XC2S300E, XC2S400E)
(Continued)
Pad Name
Function Bank Pin
LVDS
Async.
Output
Option
VREF
Option
I/O, L65P
6
L4 XC2S50E,
-
150E, 200E,
300E, 400E
I/O, VREF
6
L5 XC2S50E,
All
Bank 6, L65N
150E, 200E,
300E, 400E
I/O, L64P_YY 6 M3
All
-
I/O, L64N_YY 6 M4
All
-
I/O, L63P
6 N2 XC2S100E,
-
200E, 300E
I/O, L63N
6 N3 XC2S100E, XC2S200E,
200E, 300E 300E, 400E
I/O, L62P_YY 6 P1
All
-
I/O, L62N_YY 6 P2
All
-
M1
-
R1
-
-
M0
-
T2
-
-
M2
-
R3
-
-
I/O, L61N_YY 5
I/O, L61P_YY 5
I/O, L60N
5
I/O, L60P
5
I/O, L59N_YY 5
I/O, L59P_YY 5
I/O, VREF
5
Bank 5,
L58N_YY
I/O, L58P_YY 5
I/O, L57N
5
P4
All
-
R4
All
-
T3 XC2S50E, XC2S200E,
100E, 200E, 300E, 400E
300E, 400E
T4 XC2S50E,
-
100E, 200E,
300E, 400E
N5
All
-
P5
All
-
R5
All
All
T5
All
-
N6 XC2S50E,
-
100E, 150E,
300E
FT256 Pinouts (XC2S50E, XC2S100E,
XC2S150E, XC2S200E, XC2S300E, XC2S400E)
(Continued)
Pad Name
Function Bank Pin
LVDS
Async.
Output
Option
VREF
Option
I/O, L57P
5 P6 XC2S50E,
-
100E, 150E,
300E
I/O, L56N
5 R6 XC2S50E, XC2S100E,
100E, 200E, 150E, 200E,
300E, 400E 300E, 400E
I/O, L56P
5 T6 XC2S50E,
-
100E, 200E,
300E, 400E
I/O, L55N
5 M6 XC2S50E,
-
100E, 200E,
300E, 400E
I/O, L55P
5 N7 XC2S50E,
-
100E, 200E,
300E, 400E
I/O
5 P7
-
-
I/O, L54N
5 R7 XC2S50E,
-
200E, 300E,
400E
I/O, L54P
5 T7 XC2S50E,
-
200E, 300E,
400E
I/O, VREF
5 M7 XC2S50E,
All
Bank 5, L53N
200E, 300E,
400E
I/O, L53P
5 N8 XC2S50E,
-
200E, 300E,
400E
I/O
5 P8
-
XC2S400E
I/O (DLL),
5 R8
-
-
L52N
GCK1, I
5 T8
-
-
GCK0, I
I/O (DLL),
L52P
I/O, L51N
4 T9
-
-
4 R9
-
-
4 P9 XC2S50E, XC2S400E
150E, 200E,
400E
DS077-4 (2.3) June 18, 2008
www.xilinx.com
67
Product Specification
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