SM320F28335-EP_12 Datasheet, PDF (85/167 Pages) Texas Instruments – Digital Signal Controller (DSC)

SM320F28335-EP
www.ti.com
SPRS581D – JUNE 2009 – REVISED MAY 2012
NAME
SCIRXSTC
SCIRXEMUC
SCIRXBUFC
SCITXBUFC
SCIFFTXC ⁽²⁾
SCIFFRXC ⁽²⁾
SCIFFCTC ⁽²⁾
SCIPRC
Table 4-12. SCI-C Registers^{(1) (2)} (continued)
ADDRESS
0x7775
0x7776
0x7777
0x7779
0x777A
0x777B
0x777C
0x777F
SIZE (x16)
1
1
1
1
1
1
1
1
DESCRIPTION
SCI-C Receive Status Register
SCI-C Receive Emulation Data Buffer Register
SCI-C Receive Data Buffer Register
SCI-C Transmit Data Buffer Register
SCI-C FIFO Transmit Register
SCI-C FIFO Receive Register
SCI-C FIFO Control Register
SCI-C Priority Control Register
Figure 4-15 shows the SCI module block diagram.
Frame Format and Mode
Parity
Even/Odd Enable
SCICCR.6 SCICCR.5
TXWAKE
SCICTL1.3
1
WUT
LSPCLK
SCIHBAUD. 15 - 8
Baud Rate
MSbyte
Register
SCILBAUD. 7 - 0
Baud Rate
LSbyte
Register
SCIRXST.7 SCIRXST.4 - 2
RX Error
FE OE PE
RX Error
SCICTL1.1
TXSHF
Register
8
TXENA
Transmitter-Data
Buffer Register
8
TX FIFO _0
TX FIFO _1
TX FIFO
Interrupts
-----
TX FIFO _15
SCITXBUF.7-0
TX FIFO registers
SCITXD
TX EMPTY
SCICTL2.6
TXRDY
SCICTL2.7
TX INT ENA
SCICTL2.0
TX Interrupt
Logic
SCI TX Interrupt select logic
SCIFFENA
SCIFFTX.14
AutoBaud Detect logic
RXSHF
Register
RXENA
8 ^SCICTL1.0
Receive Data
Buffer register
SCIRXBUF.7-0
8
RX FIFO _15
-----
RX FIFO_1
RX FIFO _0
RX FIFO
Interrupts
SCIRXBUF.7-0
RX FIFO registers
RXFFOVF
SCIFFRX.15
SCIRXD
RXWAKE
SCIRXST.1
RXRDY
SCIRXST.6
SCICTL2.1
RX/BK INT ENA
BRKDT
SCIRXST.5
RX Interrupt
Logic
TXINT
To CPU
RXINT
To CPU
SCITXD
SCIRXD
RX ERR INT ENA
SCICTL1.6
SCI RX Interrupt select logic
Figure 4-15. Serial Communications Interface (SCI) Module Block Diagram
Copyright © 2009–2012, Texas Instruments Incorporated
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Peripherals
85