SM320F28335-EP_12 Datasheet, PDF (84/167 Pages) Texas Instruments – Digital Signal Controller (DSC)

SM320F28335-EP
SPRS581D – JUNE 2009 – REVISED MAY 2012
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The SCI port operation is configured and controlled by the registers listed in Table 4-10, Table 4-11, and
Table 4-12.
Table 4-10. SCI-A Registers⁽¹⁾
NAME
ADDRESS
SIZE (x16)
DESCRIPTION
SCICCRA
0x7050
1
SCI-A Communications Control Register
SCICTL1A
0x7051
1
SCI-A Control Register 1
SCIHBAUDA
0x7052
1
SCI-A Baud Register, High Bits
SCILBAUDA
0x7053
1
SCI-A Baud Register, Low Bits
SCICTL2A
0x7054
1
SCI-A Control Register 2
SCIRXSTA
0x7055
1
SCI-A Receive Status Register
SCIRXEMUA
0x7056
1
SCI-A Receive Emulation Data Buffer Register
SCIRXBUFA
0x7057
1
SCI-A Receive Data Buffer Register
SCITXBUFA
SCIFFTXA ⁽²⁾
SCIFFRXA ⁽²⁾
SCIFFCTA ⁽²⁾
0x7059
0x705A
0x705B
0x705C
1
SCI-A Transmit Data Buffer Register
1
SCI-A FIFO Transmit Register
1
SCI-A FIFO Receive Register
1
SCI-A FIFO Control Register
SCIPRIA
0x705F
1
SCI-A Priority Control Register
(1) Registers in this table are mapped to Peripheral Frame 2 space. This space only allows 16-bit accesses. 32-bit accesses produce
undefined results.
(2) These registers are new registers for the FIFO mode.
Table 4-11. SCI-B Registers^{(1) (2)}
NAME
ADDRESS
SIZE (x16)
DESCRIPTION
SCICCRB
0x7750
1
SCI-B Communications Control Register
SCICTL1B
0x7751
1
SCI-B Control Register 1
SCIHBAUDB
0x7752
1
SCI-B Baud Register, High Bits
SCILBAUDB
0x7753
1
SCI-B Baud Register, Low Bits
SCICTL2B
0x7754
1
SCI-B Control Register 2
SCIRXSTB
0x7755
1
SCI-B Receive Status Register
SCIRXEMUB
0x7756
1
SCI-B Receive Emulation Data Buffer Register
SCIRXBUFB
0x7757
1
SCI-B Receive Data Buffer Register
SCITXBUFB
SCIFFTXB ⁽²⁾
SCIFFRXB ⁽²⁾
SCIFFCTB ⁽²⁾
0x7759
0x775A
0x775B
0x775C
1
SCI-B Transmit Data Buffer Register
1
SCI-B FIFO Transmit Register
1
SCI-B FIFO Receive Register
1
SCI-B FIFO Control Register
SCIPRIB
0x775F
1
SCI-B Priority Control Register
(1) Registers in this table are mapped to Peripheral Frame 2 space. This space only allows 16-bit accesses. 32-bit accesses produce
undefined results.
(2) These registers are new registers for the FIFO mode.
Table 4-12. SCI-C Registers^{(1) (2)}
NAME
SCICCRC
SCICTL1C
SCIHBAUDC
SCILBAUDC
SCICTL2C
ADDRESS
0x7770
0x7771
0x7772
0x7773
0x7774
SIZE (x16)
1
1
1
1
1
DESCRIPTION
SCI-C Communications Control Register
SCI-C Control Register 1
SCI-C Baud Register, High Bits
SCI-C Baud Register, Low Bits
SCI-C Control Register 2
(1) Registers in this table are mapped to Peripheral Frame 2 space. This space only allows 16-bit accesses. 32-bit accesses produce
undefined results.
(2) These registers are new registers for the FIFO mode.
84
Peripherals
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