SM320F28335-EP_12 Datasheet, PDF (138/167 Pages) Texas Instruments – Digital Signal Controller (DSC)

SM320F28335-EP
SPRS581D – JUNE 2009 – REVISED MAY 2012
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(A) (B)
Lead
WS (Synch)
(C)
Active
Trail
XCLKOUT = XTIMCLK
XCLKOUT = 1/2 XTIMCLK
XZCS0 XZCS6, XZCS7
XA[0:19]
XRD
XWE0, XWE1 ^(D)
XR/W
XD[0:31], XD[0:15]
t_{d(XCOH-XZCSL)}
t_d(XCOH-XA)
t_{d(XCOHL-XRDL)}
t_su(XD)XRD
t_a(XRD)
t_a(A)
t_{su(XRDYsynchL)XCOHL}
t_{d(XCOHL-XZCSH)}
t_{d(XCOHL-XRDH)}
DIN
t_h(XD)XRD
XREADY(Synch)
t_{h(XRDYsynchL)}
t_{su(XRDHsynchH)XCOHL}
(E)
(F)
t_{e(XRDYsynchH)}
t_{h(XRDYsynchH)XZCSH}
Legend:
= Don’t care. Signal can be high or low during this time.
A. All XINTF accesses (lead period) begin on the rising edge of XCLKOUT. When necessary, the device inserts an
alignment cycle before an access to meet this requirement.
B. During alignment cycles, all signals transition to their inactive state.
C. During inactive cycles, the XINTF address bus always holds the last address put out on the bus except XA0, which
remains high. This includes alignment cycles.
D. XWE1 is valid only in 32-bit data bus mode. In 16-bit mode, this signal is XA0.
E. For each sample, setup time from the beginning of the access (E) can be calculated as:
D = (XRDLEAD + XRDACTIVE +n - 1) t_c(XTIM) – t_{su(XRDYsynchL)XCOHL}
F. Reference for the first sample is with respect to this point: F = (XRDLEAD + XRDACTIVE) t_c(XTIM) where n is the
sample number: n = 1, 2, 3, and so forth.
Figure 6-26. Example Read With Synchronous XREADY Access
XTIMING register parameters used for this example :
XRDLEAD XRDACTIVE XRDTRAIL USEREADY X2TIMING
≥1
3
≥1
1
0
XWRLEAD
N/A ⁽¹⁾
(1) N/A = “Don’t care” for this example
XWRACTIVE
N/A ⁽¹⁾
XWRTRAIL
N/A ⁽¹⁾
READYMODE
0 = XREADY
(Synch)
138 Electrical Specifications
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