SM320F28335-EP_12 Datasheet, PDF (155/167 Pages) Texas Instruments – Digital Signal Controller (DSC)

SM320F28335-EP
www.ti.com
SPRS581D – JUNE 2009 – REVISED MAY 2012
For all SPI slave modes, CLKX has to be minimum 8 CLKG cycles. Also CLKG should be LSPCLK/2 by
setting CLKSM = CLKGDV = 1. With maximum LSPCLK speed of 75 MHz, CLKX maximum frequency will
be LSPCLK/16 , that is 4.6875 MHz and P = 13.3 ns.
CLKX
LSB
M32
MSB
M33
M24
FSX
M28
M25
M29
DX
Bit 0
DR
Bit 0
Bit(n-1)
(n-2)
M30
M31
(n-3)
(n-4)
Bit(n-1)
(n-2)
(n-3)
(n-4)
Figure 6-38. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0
Table 6-58. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 0)
NO.
M39 t_su(DRV-CKXH)
M40 t_h(CKXH-DRV)
M41 t_su(FXL-CKXH)
M42 t_c(CKX)
(1) 2P = 1/CLKG
Setup time, DR valid before CLKX high
Hold time, DR valid after CLKX high
Setup time, FSX low before CLKX high
Cycle time, CLKX
MASTER
SLAVE
MIN
MAX
MIN MAX
30
8P – 10
1
8P – 10
2P ⁽¹⁾
16P + 10
16P
UNIT
ns
ns
ns
ns
Table 6-59. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 0)
NO.
PARAMETER
M34
M35
M37
t_h(CKXL-FXL)
t_d(FXL-CKXH)
t_{dis(CKXL-DXHZ)}
M38
t_d(FXL-DXV)
(1) 2P = 1/CLKG
Hold time, FSX low after CLKX low
Delay time, FSX low to CLKX high
Disable time, DX high impedance following last data bit
from CLKX low
Delay time, FSX low to DX valid
MASTER
MIN
MAX
P
2P ⁽¹⁾
P+6
SLAVE
MIN MAX
7P + 6
UNIT
ns
ns
ns
6
4P + 6
ns
For all SPI slave modes, CLKX must be a minimum of 8 CLKG cycles. Also, CLKG should be LSPCLK/2
by setting CLKSM = CLKGDV = 1. With a maximum LSPCLK speed of 75 MHz, CLKX maximum
frequency is LSPCLK/16; that is, 4.6875 MHz and P =13.3 ns.
CLKX
LSB
M41
MSB
M42
M34
FSX
M37
DX
Bit 0
DR
Bit 0
M35
M38
M39
Bit(n-1)
Bit(n-1)
(n-2)
M40
(n-2)
(n-3)
(n-3)
(n-4)
(n-4)
Figure 6-39. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0
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Electrical Specifications 155