SM320F28335-EP_12 Datasheet, PDF (37/167 Pages) Texas Instruments – Digital Signal Controller (DSC)

SM320F28335-EP
www.ti.com
SPRS581D – JUNE 2009 – REVISED MAY 2012
3.2.4 Real-Time JTAG and Analysis
The F28335 implements the standard IEEE 1149.1 JTAG interface. Additionally, the device supports real-
time mode of operation whereby the contents of memory, peripheral and register locations can be
modified while the processor is running and executing code and servicing interrupts. The user can also
single step through non-time critical code while enabling time-critical interrupts to be serviced without
interference. The device implements the real-time mode in hardware within the CPU. This is a feature
unique to the F28335, requiring no software monitor. Additionally, special analysis hardware is provided
that allows setting of hardware breakpoint or data/address watch-points and generate various user-
selectable break events when a match occurs.
3.2.5 External Interface (XINTF)
This asynchronous interface consists of 20 address lines, 32 data lines, and three chip-select lines. The
chip-select lines are mapped to three external zones, Zones 0, 6, and 7. Each of the three zones can be
programmed with a different number of wait states, strobe signal setup and hold timing and each zone can
be programmed for extending wait states externally or not. The programmable wait-state, chip-select and
programmable strobe timing enables glueless interface to external memories and peripherals.
3.2.6 Flash
The F28335 contains 256K × 16 of embedded flash memory, segregated into eight 32K × 16 sectors and
a single 1K × 16 of OTP memory at address range 0x380400 – 0x3807FF. The user can individually
erase, program, and validate a flash sector while leaving other sectors untouched. However, it is not
possible to use one sector of the flash or the OTP to execute flash algorithms that erase/program other
sectors. Special memory pipelining is provided to enable the flash module to achieve higher performance.
The flash/OTP is mapped to both program and data space; therefore, it can be used to execute code or
store data information. Note that addresses 0x33FFF0 – 0x33FFF5 are reserved for data variables and
should not contain program code.
NOTE
The Flash and OTP wait-states can be configured by the application. This allows applications
running at slower frequencies to configure the flash to use fewer wait-states.
Flash effective performance can be improved by enabling the flash pipeline mode in the
Flash options register. With this mode enabled, effective performance of linear code
execution will be much faster than the raw performance indicated by the wait-state
configuration alone. The exact performance gain when using the Flash pipeline mode is
application-dependent.
3.2.7 M0, M1 SARAMs
The F28335 contains these two blocks of single access memory, each 1K × 16 in size. The stack pointer
points to the beginning of block M1 on reset. The M0 and M1 blocks, like all other memory blocks on C28x
devices, are mapped to both program and data space. Hence, the user can use M0 and M1 to execute
code or for data variables. The partitioning is performed within the linker. The C28x device presents a
unified memory map to the programmer. This makes for easier programming in high-level languages.
3.2.8 L0, L1, L2, L3, L4, L5, L6, L7 SARAMs
The F28335 contains an additional 32K × 16 of single-access RAM, divided into 8 blocks (L0-L7 with 4K
each). Each block can be independently accessed to minimize CPU pipeline stalls. Each block is mapped
to both program and data space. L4, L5, L6, and L7 are DMA accessible.
Copyright © 2009–2012, Texas Instruments Incorporated
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Functional Overview
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