SM320F28335-EP_12 Datasheet, PDF (117/167 Pages) Texas Instruments – Digital Signal Controller (DSC)

SM320F28335-EP
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SPRS581D – JUNE 2009 – REVISED MAY 2012
Table 6-16. STANDBY Mode Switching Characteristics
PARAMETER
TEST CONDITIONS
MIN TYP
MAX UNIT
t_d(IDLE-XCOL)
Delay time, IDLE instruction
executed to XCLKOUT low
32t_c(SCO)
45t_c(SCO) cycles
t_d(WAKE-STBY)
Delay time, external wake
signal to program execution
resume ⁽¹⁾
cycles
• Wake up from flash
Without input qualifier
–
Flash module in active
state
With input qualifier
100t_c(SCO)
100t_c(SCO) + t_w(WAKE-INT)
cycles
• Wake up from flash
Without input qualifier
– Flash module in sleep
state
With input qualifier
1125t_c(SCO)
1125t_c(SCO) + t_w(WAKE-INT)
cycles
• Wake up from SARAM
Without input qualifier
With input qualifier
100t_c(SCO)
100t_c(SCO) + t_w(WAKE-INT)
cycles
(1) This is the time taken to begin execution of the instruction that immediately follows the IDLE instruction. execution of an ISR (triggered
by the wake up signal) involves additional latency.
Device
Status
Wake−up
Signal
(A)
(B)
Flushing Pipeline
X1/X2 or
X1 or
XCLKIN
(C)
STANDBY
(D)
STANDBY
(E)
(F)
Normal Execution
t_w(WAKE-INT)
t_d(WAKE-STBY)
XCLKOUT
t_{d(IDLE−XCOL)}
A. IDLE instruction is executed to put the device into STANDBY mode.
B. The PLL block responds to the STANDBY signal. SYSCLKOUT is held for the number of cycles indicated below
before being turned off:
• 16 cycles, when DIVSEL = 00 or 01
• 32 cycles, when DIVSEL = 10
• 64 cycles, when DIVSEL = 11
This delay enables the CPU pipeline and any other pending operations to flush properly. If an access to XINTF is
in progress and its access time is longer than this number then it will fail.� It is recommended to enter STANDBY
mode from SARAM without an XINTF access in progress.
C. Clock to the peripherals are turned off. However, the PLL and watchdog are not shut down. The device is now in
STANDBY mode.
D. The external wake-up signal is driven active.
E. After a latency period, the STANDBY mode is exited.
F. Normal execution resumes. The device will respond to the interrupt (if enabled).
Figure 6-14. STANDBY Entry and Exit Timing Diagram
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Electrical Specifications 117