SM320F28335-EP_12 Datasheet, PDF (141/167 Pages) Texas Instruments – Digital Signal Controller (DSC)

SM320F28335-EP
www.ti.com
SPRS581D – JUNE 2009 – REVISED MAY 2012
(A) (B)
(D)
XCLKOUT = XTIMCLK
Lead 1
WS (Synch)
Active
Trail
(C)
XZCS0AND1, XZCS2,
XZCS6AND7
XA[0:18]
XRD
XWE
XR/W
XD[0:15]
t_{d(XCOH-XZCSL)}
t_d(XCOH-XA)
t_{d(XCOH-XRNWL)}
t_{d(XCOHL-XWEL)}
t_en(XD)XWEL
t_d(XWEL-XD
)
t_{d(XCOHL-XZCSH)}
t_{h(XRDYsynchH)XZCSH}
t_{d(XCOHL-XWEH)}
t_{d(XCOHL-XRNWH)}
DOUT
t_dis(XD)XRNW
t_h(XD)XWEH
t_{su(XRDYsynchL)XCOHL}
t_{h(XRDYsynchL)}
t_{su(XRDHsynchH)XCOHL}
XREADY(Synch)
(E)
(F)
Legend:
= Don’t care. Signal can be high or low during this time.
A. All XINTF accesses (lead period) begin on the rising edge of XCLKOUT. When necessary, the device inserts an
alignment cycle before an access to meet this requirement.
B. During alignment cycles, all signals will transition to their inactive state.
C. During inactive cycles, the XINTF address bus always holds the last address put out on the bus except XA0, which
remains high. This includes alignment cycles.
D. XWE1 is used in 32-bit data bus mode only. In 16-bit, this signal is XA0
E. For each sample, setup time from the beginning of the access can be calculated as E = (XWRLEAD + XWRACTIVE +
n –1) t_c(XTIM) – t_{su(XRDYsynchL)XCOH} where n is the sample number: n = 1, 2, 3, and so forth.
F. Reference for the first sample is with respect to this point: F = (XWRLEAD + XWRACTIVE) t_c(XTIM)
Figure 6-28. Write With Synchronous XREADY Access
XTIMING register parameters used for this example :
XRDLEAD XRDACTIVE XRDTRAIL USEREADY X2TIMING
N/A ⁽¹⁾
N/A ⁽¹⁾
N/A ⁽¹⁾
1
0
XWRLEAD
≥1
(1) N/A = "Don't care" for this example.
XWRACTIVE
3
XWRTRAIL
≥1
READYMODE
0 = XREADY
(Synch)
Copyright © 2009–2012, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Link(s): SM320F28335-EP
Electrical Specifications 141