SM320F28335-EP_12 Datasheet, PDF (47/167 Pages) Texas Instruments – Digital Signal Controller (DSC)

SM320F28335-EP
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SPRS581D – JUNE 2009 – REVISED MAY 2012
INT1
INT2
INT11
INT12
IFR(12:1)
(Flag)
IER(12:1)
(Enable)
INTM
MUX
1
0
Global
Enable
CPU
INTx
MUX
PIEACKx
(Enable/Flag)
(Enable)
PIEIERx(8:1)
(Flag)
PIEIFRx(8:1)
INTx.1
INTx.2
INTx.3
INTx.4
INTx.5
INTx.6
INTx.7
INTx.8
Figure 3-5. Multiplexing of Interrupts Using the PIE Block
From
Peripherals or
External
Interrupts
Table 3-10. PIE Peripheral Interrupts⁽¹⁾
CPU INTERRUPTS
INT1
INT2
INTx.8
WAKEINT
(LPM/WD)
Reserved
INT3
Reserved
INT4
Reserved
INT5
Reserved
INT6
Reserved
INT7
Reserved
INT8
INT9
INT10
INT11
INT12
Reserved
ECAN1_INTB
(CAN-B)
Reserved
Reserved
LUF
(FPU)
INTx.7
TINT0
(TIMER 0)
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
ECAN0_INTB
(CAN-B)
Reserved
Reserved
LVF
(FPU)
INTx.6
ADCINT
(ADC)
EPWM6_TZINT
(ePWM6)
EPWM6_INT
(ePWM6)
ECAP6_INT
(ECAP6)
Reserved
MXINTA
(McBSP-A)
DINTCH6
(DMA)
SCITXINTC
(SCI-C)
ECAN1_INTA
(CAN-A)
Reserved
Reserved
Reserved
PIE INTERRUPTS
INTx.5
INTx.4
XINT2
XINT1
EPWM5_TZINT
(ePWM5)
EPWM5_INT
(ePWM5)
ECAP5_INT
(ECAP5)
EPWM4_TZINT
(ePWM4)
EPWM4_INT
(ePWM4)
ECAP4_INT
(eCAP4)
Reserved
Reserved
MRINTA
(McBSP-A)
DINTCH5
(DMA)
SCIRXINTC
(SCI-C)
ECAN0_INTA
(CAN-A)
Reserved
Reserved
MXINTB
(McBSP-B)
DINTCH4
(DMA)
Reserved
SCITXINTB
(SCI-B)
Reserved
Reserved
XINT7
XINT6
INTx.3
Reserved
EPWM3_TZINT
(ePWM3)
EPWM3_INT
(ePWM3)
ECAP3_INT
(eCAP3)
Reserved
MRINTB
(McBSP-B)
DINTCH3
(DMA)
Reserved
SCIRXINTB
(SCI-B)
Reserved
Reserved
XINT5
INTx.2
SEQ2INT
(ADC)
EPWM2_TZINT
(ePWM2)
EPWM2_INT
(ePWM2)
ECAP2_INT
(eCAP2)
EQEP2_INT
(eQEP2)
SPITXINTA
(SPI-A)
DINTCH2
(DMA)
I2CINT2A
(I2C-A)
SCITXINTA
(SCI-A)
Reserved
Reserved
XINT4
INTx.1
SEQ1INT
(ADC)
EPWM1_TZINT
(ePWM1)
EPWM1_INT
(ePWM1)
ECAP1_INT
(eCAP1)
EQEP1_INT
(eQEP1)
SPIRXINTA
(SPI-A)
DINTCH1
(DMA)
I2CINT1A
(I2C-A)
SCIRXINTA
(SCI-A)
Reserved
Reserved
XINT3
(1) Out of the 96 possible interrupts, 58 interrupts are currently used. The remaining interrupts are reserved for future devices. These
interrupts can be used as software interrupts if they are enabled at the PIEIFRx level, provided none of the interrupts within the group is
being used by a peripheral. Otherwise, interrupts coming in from peripherals may be lost by accidentally clearing their flag while
modifying the PIEIFR. To summarize, there are two safe cases when the reserved interrupts could be used as software interrupts:
1) No peripheral within the group is asserting interrupts.
2) No peripheral interrupts are assigned to the group (example PIE group 11).
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