SM320F28335-EP_12 Datasheet, PDF (53/167 Pages) Texas Instruments – Digital Signal Controller (DSC)

SM320F28335-EP
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SPRS581D – JUNE 2009 – REVISED MAY 2012
Table 3-14. PLLCR⁽¹⁾ Bit Descriptions
PLLCR[DIV] VALUE^{(2) (3)}
PLLSTS[DIVSEL] = 0 or 1
SYSCLKOUT (CLKIN)
PLLSTS[DIVSEL] = 2
PLLSTS[DIVSEL] = 3
0000 (PLL bypass)
OSCCLK/4 (Default)
OSCCLK/2
OSCCLK
0001
(OSCCLK * 1)/4
(OSCCLK * 1)/2
–
0010
(OSCCLK * 2)/4
(OSCCLK * 2)/2
–
0011
(OSCCLK * 3)/4
(OSCCLK * 3)/2
–
0100
(OSCCLK * 4)/4
(OSCCLK * 4)/2
–
0101
(OSCCLK * 5)/4
(OSCCLK * 5)/2
–
0110
(OSCCLK * 6)/4
(OSCCLK * 6)/2
–
0111
(OSCCLK * 7)/4
(OSCCLK * 7)/2
–
1000
(OSCCLK * 8)/4
(OSCCLK * 8)/2
–
1001
(OSCCLK * 9)/4
(OSCCLK * 9)/2
–
1010
(OSCCLK * 10)/4
(OSCCLK * 10)/2
–
1011 - 1111
Reserved
Reserved
Reserved
(1) By default, PLLSTS[DIVSEL] is configured for /4. (The boot ROM changes this to /2.) PLLSTS[DIVSEL] must be 0 before writing to the
PLLCR and should be changed only after PLLSTS[PLLLOCKS] = 1.
(2) The PLL control register (PLLCR) and PLL Status Register (PLLSTS) are reset to their default state by the XRS signal or a watchdog
reset only. A reset issued by the debugger or the missing clock detect logic have no effect.
(3) This register is EALLOW protected.
Table 3-15. CLKIN Divide Options
PLLSTS [DIVSEL]
CLKIN DIVIDE
0
/4
1
/4
2
/2
3
/1 ⁽¹⁾
(1) This mode can be used only when the PLL is bypassed or off.
The PLL-based clock module provides two modes of operation:
• Crystal-operation - This mode allows the use of an external crystal/resonator to provide the time base
to the device.
• External clock source operation - This mode allows the internal oscillator to be bypassed. The device
clocks are generated from an external clock source input on the X1 or the XCLKIN pin.
Table 3-16. Possible PLL Configuration Modes
PLL MODE
REMARKS
PLLSTS[DIVSEL]
Invoked by the user setting the PLLOFF bit in the PLLSTS register. The PLL block
is disabled in this mode. This can be useful to reduce system noise and for low
0, 1
PLL Off
power operation. The PLLCR register must first be set to 0x0000 (PLL Bypass)
2
before entering this mode. The CPU clock (CLKIN) is derived directly from the
3
input clock on either X1/X2, X1 or XCLKIN.
PLL Bypass
PLL Bypass is the default PLL configuration upon power-up or after an external
reset (XRS). This mode is selected when the PLLCR register is set to 0x0000 or
while the PLL locks to a new frequency after the PLLCR register has been
modified. In this mode, the PLL itself is bypassed but the PLL is not turned off.
0, 1
2
3
PLL Enable
Achieved by writing a non-zero value n into the PLLCR register. Upon writing to the
PLLCR the device will switch to PLL Bypass mode until the PLL locks.
0, 1
2
CLKIN AND
SYSCLKOUT
OSCCLK/4
OSCCLK/2
OSCCLK/1
OSCCLK/4
OSCCLK/2
OSCCLK/1
OSCCLK*n/4
OSCCLK*n/2
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Functional Overview
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