SM320F28335-EP_12 Datasheet, PDF (142/167 Pages) Texas Instruments – Digital Signal Controller (DSC)

SM320F28335-EP
SPRS581D – JUNE 2009 – REVISED MAY 2012
www.ti.com
(A) (B)
Lead 1
WS (Async)
Active
Trail
(C)
XCLKOUT = XTIMCLK
XCLKOUT = 1/2 XTIMCLK
XZCS0, XZCS6, XZCS7
XA[0:19]
XRD
XWE0, XWE1^(D)
XR/W
XD[31:0], XD[15:0]
XREADY(Asynch)
t_{d(XCOH-XZCSL)}
t_d(XCOH-XA)
t_{d(XCOHL-XZCSH)}
t_{h(XRDYasynchH)XZCSH}
t_{d(XCOH-XRNWL)}
t_{d(XCOHL-XWEL)}
t_{d(XCOHL-XWEH)}
t_{d(XCOHL-XRNWH)}
t_en(XD)XWEL
t_d(XWEL-XD
)
DOUT
t_{su(XRDYasynchL)XCOHL}
t_{h(XRDYasynchL)}
t_{e(XRDYasynchH)}
t_{su(XRDYasynchH)XCOHL}
t_dis(XD)XRNW
t_h(XD)XWEH
(D)
(E)
Legend:
= Don’t care. Signal can be high or low during this time.
A. All XINTF accesses (lead period) begin on the rising edge of XCLKOUT. When necessary, the device inserts an
alignment cycle before an access to meet this requirement.
B. During alignment cycles, all signals transition to their inactive state.
C. During inactive cycles, the XINTF address bus always holds the last address put out on the bus except XA0, which
remains high. This includes alignment cycles.
D. XWE1 is used in 32-bit data bus mode only. In 16-bit, this signal is XA0.
E. For each sample, set up time from the beginning of the access can be calculated as: E = (XWRLEAD + XWRACTIVE
-3 + n) t_c(XTIM) – t_{su(XRDYasynchL)XCOHL} where n is the sample number: n = 1, 2, 3, and so forth.
F. Reference for the first sample is with respect to this point: F = (XWRLEAD + XWRACTIVE – 2) t_c(XTIM)
Figure 6-29. Write With Asynchronous XREADY Access
XTIMING register parameters used for this example :
XRDLEAD XRDACTIVE
XRDTRAIL
USEREADY X2TIMING
N/A ⁽¹⁾
N/A ⁽¹⁾
N/A ⁽¹⁾
1
0
XWRLEAD
≥1
XWRACTIVE
3
XWRTRAIL
≥1
(1) N/A = “Don’t care” for this example
READYMODE
1 = XREADY
(Async)
142 Electrical Specifications
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