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SM320F28335-EP_12 Datasheet, PDF (81/167 Pages) Texas Instruments – Digital Signal Controller (DSC) | |||
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SM320F28335-EP
www.ti.com
SPRS581D â JUNE 2009 â REVISED MAY 2012
6200h
623Fh
6240h
627Fh
6280h
62BFh
62C0h
62FFh
eCAN-B Memory (512 Bytes)
Control and Status Registers
Local Acceptance Masks (LAM)
(32 Ã 32-Bit RAM)
Message Object Time Stamps (MOTS)
(32 Ã 32-Bit RAM)
Message Object Time-Out (MOTO)
(32 Ã 32-Bit RAM)
6300hâ6307h
6308hâ630Fh
6310hâ6317h
6318hâ631Fh
6320hâ6327h
eCAN-B Memory RAM (512 Bytes)
Mailbox 0
Mailbox 1
Mailbox 2
Mailbox 3
Mailbox 4
eCAN-B Control and Status Registers
Mailbox Enable â CANME
Mailbox Direction â CANMD
Transmission Request Set â CANTRS
Transmission Request Reset â CANTRR
Transmission Acknowledge â CANTA
Abort Acknowledge â CANAA
Received Message Pending â CANRMP
Received Message Lost â CANRML
Remote Frame Pending â CANRFP
Global Acceptance Mask â CANGAM
Master Control â CANMC
Bit-Timing Configuration â CANBTC
Error and Status â CANES
Transmit Error Counter â CANTEC
Receive Error Counter â CANREC
Global Interrupt Flag 0 â CANGIF0
Global Interrupt Mask â CANGIM
Global Interrupt Flag 1 â CANGIF1
Mailbox Interrupt Mask â CANMIM
Mailbox Interrupt Level â CANMIL
Overwrite Protection Control â CANOPC
TX I/O Control â CANTIOC
RX I/O Control â CANRIOC
Time Stamp Counter â CANTSC
Time-Out Control â CANTOC
Time-Out Status â CANTOS
63E0hâ63E7h
63E8hâ63EFh
63F0hâ63F7h
63F8hâ63FFh
Mailbox 28
Mailbox 29
Mailbox 30
Mailbox 31
Reserved
63E8hâ63E9h
63EAhâ63EBh
63EChâ63EDh
63EEhâ63EFh
Message Mailbox (16 Bytes)
Message Identifier â MSGID
Message Control â MSGCTRL
Message Data Low â MDL
Message Data High â MDH
Figure 4-14. eCAN-B Memory Map
The CAN registers listed in Table 4-9 are used by the CPU to configure and control the CAN controller
and the message objects. eCAN control registers only support 32-bit read/write operations. Mailbox RAM
can be accessed as 16 bits or 32 bits. 32-bit accesses are aligned to an even boundary.
Copyright © 2009â2012, Texas Instruments Incorporated
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