SM320F28335-EP_12 Datasheet, PDF (52/167 Pages) Texas Instruments – Digital Signal Controller (DSC)

SM320F28335-EP
SPRS581D – JUNE 2009 – REVISED MAY 2012
XCLKIN
X1 X2
External Clock Signal
NC
(Toggling 0 −V_DDIO)
Figure 3-8. Using a 3.3-V External Oscillator
XCLKIN
X1
X2
External Clock Signal
NC
(Toggling 0 −V_DD)
Figure 3-9. Using a 1.9-V External Oscillator
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XCLKIN
X1
X2
C_L1
C_L2
Crystal
Figure 3-10. Using the Internal Oscillator
3.6.1.1 External Reference Oscillator Clock Option
The typical specifications for the external quartz crystal for a frequency of 30 MHz are listed below:
• Fundamental mode, parallel resonant
• C_L (load capacitance) = 12 pF
• C_L1 = C_L2 = 24 pF
• C_shunt = 6 pF
• ESR range = 25 to 40 Ω
TI recommends that customers have the resonator/crystal vendor characterize the operation of their
device with the DSC chip. The resonator/crystal vendor has the equipment and expertise to tune the tank
circuit. The vendor can also advise the customer regarding the proper tank component values that will
produce proper start up and stability over the entire operating range.
3.6.1.2 PLL-Based Clock Module
The devices have an on-chip, PLL-based clock module. This module provides all the necessary clocking
signals for the device, as well as control for low-power mode entry. The PLL has a 4-bit ratio control
PLLCR[DIV] to select different CPU clock rates. The watchdog module should be disabled before writing
to the PLLCR register. It can be re-enabled (if need be) after the PLL module has stabilized, which takes
131072 OSCCLK cycles. The input clock and PLLCR[DIV] bits should be chosen in such a way that the
output frequency of the PLL (VCOCLK) does not exceed 300 MHz.
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Functional Overview
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