SM320F28335-EP_12 Datasheet, PDF (147/167 Pages) Texas Instruments – Digital Signal Controller (DSC)

SM320F28335-EP
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6.15.1 ADC Power-Up Control Bit Timing
ADC Power Up Delay
PWDNBG
SPRS581D – JUNE 2009 – REVISED MAY 2012
ADC Ready for Conversions
PWDNREF
PWDNADC
Request for
ADC
Conversion
t_d(BGR)
t_d(PWD)
Figure 6-32. ADC Power-Up Control Bit Timing
Table 6-50. ADC Power-Up Delays
PARAMETER ⁽¹⁾
MIN TYP MAX
UNIT
t_d(BGR)
Delay time for band gap reference to be stable. Bits 7 and 6 of the ADCTRL3
register (ADCBGRFDN1/0) must be set to 1 before the PWDNADC bit is enabled.
5
ms
t_d(PWD)
Delay time for power-down control to be stable. Bit delay time for band-gap
20
50
μs
reference to be stable. Bits 7 and 6 of the ADCTRL3 register (ADCBGRFDN1/0)
must be set to 1 before the PWDNADC bit is enabled. Bit 5 of the ADCTRL3
1
ms
register (PWDNADC)must be set to 1 before any ADC conversions are initiated.
(1) Timings maintain compatibility to the 281x ADC module. The 2833x/2823x ADC also supports driving all 3 bits at the same time and
waiting t_d(BGR) ms before first conversion.
Table 6-51. Typical Current Consumption for Different ADC Configurations (at 25-MHz ADCCLK)^{(1) (2)}
ADC OPERATING MODE
Mode A (Operational Mode): _•
•
CONDITIONS
BG and REF enabled
PWD disabled
V_DDA18
30
Mode B:
• ADC clock enabled
9
• BG and REF enabled
• PWD enabled
Mode C:
• ADC clock enabled
5
• BG and REF disabled
• PWD enabled
Mode D:
• ADC clock disabled
5
• BG and REF disabled
• PWD enabled
(1) Test Conditions:
SYSCLKOUT = 150 MHz
ADC module clock = 25 MHz
ADC performing a continuous conversion of all 16 channels in Mode A
(2) V_DDA18 includes current into V_DD1A18 and V_DD2A18. V_DDA3.3 includes current into V_DDA2 and V_DDAIO.
V_DDA3.3
2
0.5
UNIT
mA
mA
20
μA
15
μA
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Electrical Specifications 147