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| SM320F28335-EP_12 Datasheet, PDF (125/167 Pages) Texas Instruments – Digital Signal Controller (DSC) | |||
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SPICLK
(clock polarity = 0)
SPICLK
(clock polarity = 1)
SPISIMO
SPISOMI
1
2
3
4
5
Master Out Data Is Valid
8
9
Master In Data
Must Be Valid
SM320F28335-EP
SPRS581D â JUNE 2009 â REVISED MAY 2012
SPISTE(A)
A. In the master mode, SPISTE goes active 0.5tc(SPC) (minimum) before valid SPI clock edge. On the trailing end of the word, the SPISTE will go inactive 0.5tc(SPC) after
the receiving edge (SPICLK) of the last data bit, except that SPISTE stays active between back-to-back transmit words in both FIFO and nonFIFO modes.
Figure 6-19. SPI Master Mode External Timing (Clock Phase = 0)
Copyright © 2009â2012, Texas Instruments Incorporated
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Product Folder Link(s): SM320F28335-EP
Electrical Specifications 125
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