SM320F28335-EP_12 Datasheet, PDF (140/167 Pages) Texas Instruments – Digital Signal Controller (DSC)

SM320F28335-EP
SPRS581D – JUNE 2009 – REVISED MAY 2012
www.ti.com
6.14.8 External Interface Ready-on-Write Timing With One External Wait State
Table 6-44. External Interface Write Switching Characteristics (Ready-on-Write, 1 Wait State)
PARAMETER
MIN
MAX UNIT
t_{d(XCOH-XZCSL)}
t_{d(XCOHL-XZCSH)}
t_d(XCOH-XA)
t_{d(XCOHL-XWEL)}
t_{d(XCOHL-XWEH)}
t_{d(XCOH-XRNWL)}
t_{d(XCOHL-XRNWH)}
t_en(XD)XWEL
t_d(XWEL-XD)
t_h(XA)XZCSH
t_h(XD)XWE
t_dis(XD)XRNW
Delay time, XCLKOUT high to zone chip-select active low
Delay time, XCLKOUT high or low to zone chip-select inactive high
Delay time, XCLKOUT high to address valid
Delay time, XCLKOUT high/low to XWE0, XWE1 low⁽¹⁾
Delay time, XCLKOUT high/low to XWE0, XWE1 high⁽¹⁾
Delay time, XCLKOUT high to XR/W low
Delay time, XCLKOUT high/low to XR/W high
Enable time, data bus driven from XWE0, XWE1 low⁽¹⁾
Delay time, data valid after XWE0, XWE1 active low⁽¹⁾
Hold time, address valid after zone chip-select inactive high
Hold time, write data valid after XWE0, XWE1 inactive high⁽¹⁾
Maximum time for DSP to release the data bus after XR/W inactive high
–1
–1
0
(2)
TW-2 ⁽³⁾
1
ns
0.5
ns
1.5
ns
2
ns
2
ns
1
ns
0.5
ns
ns
1
ns
ns
ns
4
ns
(1) XWE1 is used in 32-bit data bus mode only. In 16-bit, this signal is XA0.
(2) During inactive cycles, the XINTF address bus always holds the last address put out on the bus except XA0, which remains high. This
includes alignment cycles.
(3) TW = trail period, write access (see Table 6-35)
Table 6-45. Synchronous XREADY Timing Requirements (Ready-on-Write, 1 Wait State)⁽¹⁾
MIN
MAX UNIT
t_{su(XRDYsynchL)XCOHL}
t_{h(XRDYsynchL)}
t_{e(XRDYsynchH)}
Setup time, XREADY (synchronous) low before XCLKOUT high/low
Hold time, XREADY (synchronous) low
Earliest time XREADY (synchronous) can go high before the sampling
XCLKOUT edge
12
ns
6
ns
3
ns
t_{su(XRDYsynchH)XCOHL}
Setup time, XREADY (synchronous) high before XCLKOUT high/low
12
ns
t_{h(XRDYsynchH)XZCSH}
Hold time, XREADY (synchronous) held high after zone chip select high
0
ns
(1) The first XREADY (synchronous) sample occurs with respect to E in Figure 6-28:
E =(XWRLEAD + XWRACTIVE) t_c(XTIM)
When first sampled, if XREADY (synchronous) is high, then the access will complete. If XREADY (synchronous) is low, it is sampled
again each t_c(XTIM) until it is high.
For each sample, setup time from the beginning of the access can be calculated as:
F = (XWRLEAD + XWRACTIVE +n –1) t_c(XTIM) – t_{su(XRDYsynchL)XCOHL}
where n is the sample number: n = 1, 2, 3, and so forth.
Table 6-46. Asynchronous XREADY Timing Requirements (Ready-on-Write, 1 Wait State)⁽¹⁾
MIN
MAX UNIT
t_{su(XRDYasynchL)XCOHL}
t_{h(XRDYasynchL)}
t_{e(XRDYasynchH)}
Setup time, XREADY (asynchronous) low before XCLKOUT high/low
Hold time, XREADY (asynchronous) low
Earliest time XREADY (asynchronous) can go high before the sampling
XCLKOUT edge
11
ns
6
ns
3 ns
t_{su(XRDYasynchH)XCOHL}
Setup time, XREADY (asynchronous) high before XCLKOUT high/low
11
ns
t_{h(XRDYasynchH)XZCSH}
Hold time, XREADY (asynchronous) held high after zone chip select high
0
ns
(1) The first XREADY (synchronous) sample occurs with respect to E in Figure 6-28:
E = (XWRLEAD + XWRACTIVE –2) t_c(XTIM). When first sampled, if XREADY (asynchronous) is high, then the access will complete. If
XREADY (asynchronous) is low, it is sampled again each t_c(XTIM) until it is high.
For each sample, setup time from the beginning of the access can be calculated as:
F = (XWRLEAD + XWRACTIVE –3 + n) t_c(XTIM) – t_{su(XRDYasynchL)XCOHL}
where n is the sample number: n = 1, 2, 3, and so forth.
140 Electrical Specifications
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