SM320F28335-EP_12 Datasheet, PDF (7/167 Pages) Texas Instruments – Digital Signal Controller (DSC)

SM320F28335-EP
www.ti.com
SPRS581D – JUNE 2009 – REVISED MAY 2012
List of Tables
2-1 Hardware Features .............................................................................................................. 12
2-2 Signal Descriptions............................................................................................................... 22
3-1 Addresses of Flash Sectors .................................................................................................... 34
3-2 Handling Security Code Locations ............................................................................................. 34
3-3 Wait-states ........................................................................................................................ 35
3-4 Boot Mode Selection............................................................................................................. 38
3-5 Peripheral Frame 0 Registers .................................................................................................. 43
3-6 Peripheral Frame 1 Registers .................................................................................................. 43
3-7 Peripheral Frame 2 Registers .................................................................................................. 44
3-8 Peripheral Frame 3 Registers .................................................................................................. 44
3-9 Device Emulation Registers..................................................................................................... 44
3-10 PIE Peripheral Interrupts ....................................................................................................... 47
3-11 PIE Configuration and Control Registers...................................................................................... 48
3-12 External Interrupt Registers..................................................................................................... 48
3-13 PLL, Clocking, Watchdog, and Low-Power Mode Registers ............................................................... 51
3-14 PLLCR Bit Descriptions ......................................................................................................... 53
3-15 CLKIN Divide Options ........................................................................................................... 53
3-16 Possible PLL Configuration Modes ............................................................................................ 53
3-17 Low-Power Modes ............................................................................................................... 55
4-1 CPU-Timers 0, 1, 2 Configuration and Control Registers................................................................... 59
4-2 ePWM Control and Status Registers (default configuration in PF1)....................................................... 61
4-3 ePWM Control and Status Registers (remapped configuration in PF3 - DMA accessible)............................. 62
4-4 eCAP Control and Status Registers ........................................................................................... 67
4-5 eQEP Control and Status Registers ........................................................................................... 69
4-6 ADC Registers ................................................................................................................... 73
4-7 McBSP Register Summary...................................................................................................... 77
4-8 3.3-V eCAN Transceivers ...................................................................................................... 79
4-9 CAN Register Map .............................................................................................................. 82
4-10 SCI-A Registers .................................................................................................................. 84
4-11 SCI-B Registers .................................................................................................................. 84
4-12 SCI-C Registers ................................................................................................................. 84
4-13 SPI-A Registers................................................................................................................... 87
4-14 I2C-A Registers................................................................................................................... 90
4-15 GPIO Registers .................................................................................................................. 92
4-16 GPIO-A Mux Peripheral Selection Matrix .................................................................................... 93
4-17 GPIO-B Mux Peripheral Selection Matrix .................................................................................... 94
4-18 GPIO-C Mux Peripheral Selection Matrix .................................................................................... 95
4-19 XINTF Configuration and Control Register Mapping ........................................................................ 98
6-1 Current Consumption by Power-Supply Pins at 150-MHz SYSCLKOUT ............................................... 102
6-2 Typical Current Consumption by Various Peripherals (at 150 MHz) .................................................... 103
6-3 Clocking and Nomenclature (150-MHz devices)............................................................................ 108
6-4 Clocking and Nomenclature (100-MHz devices)............................................................................ 108
6-5 Input Clock Frequency ......................................................................................................... 109
6-6 XCLKIN Timing Requirements - PLL Enabled ............................................................................. 109
6-7 XCLKIN Timing Requirements - PLL Disabled ............................................................................. 109
6-8 XCLKOUT Switching Characteristics (PLL Bypassed or Enabled) ...................................................... 109
6-9 Power Management and Supervisory Circuit Solutions ................................................................... 110
Copyright © 2009–2012, Texas Instruments Incorporated
List of Tables
7