SM320F28335-EP_12 Datasheet, PDF (127/167 Pages) Texas Instruments – Digital Signal Controller (DSC)

SM320F28335-EP
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SPRS581D – JUNE 2009 – REVISED MAY 2012
SPICLK
(clock polarity = 0)
SPICLK
(clock polarity = 1)
SPISIMO
SPISOMI
1
2
6
7
Master Out Data Is Valid
10
11
Master In Data Must
Be Valid
3
Data Valid
SPISTE^(A)
A. In the master mode, SPISTE goes active 0.5t_c(SPC) (minimum) before valid SPI clock edge. On the trailing end of the word, the SPISTE will go inactive 0.5t_c(SPC) after
the receiving edge (SPICLK) of the last data bit, except that SPISTE stays active between back-to-back transmit words in both FIFO and nonFIFO modes.
Figure 6-20. SPI Master Mode External Timing (Clock Phase = 1)
6.13.2 SPI Slave Mode Timing
Table 6-33 lists the slave mode external timing (clock phase = 0) and Table 6-34 (clock phase = 1). Figure 6-21 and Figure 6-22 show the timing
waveforms.
Table 6-33. SPI Slave Mode External Timing (Clock Phase = 0)^{(1) (2) (3) (4) (5)}
NO.
12 t_c(SPC)S
Cycle time, SPICLK
(1) The MASTER / SLAVE bit (SPICTL.2) is cleared and the CLOCK PHASE bit (SPICTL.3) is cleared.
(2) t_c(SPC) = SPI clock cycle time = LSPCLK/4 or LSPCLK/(SPIBRR + 1)
(3) Internal clock prescalers must be adjusted such that the SPI clock speed is limited to the following SPI clock rate:
Master mode transmit 25-MHz MAX, master mode receive 12.5-MHz MAX
Slave mode transmit 12.5-MHz MAX, slave mode receive 12.5-MHz MAX.
(4) t_c(LCO) = LSPCLK cycle time
(5) The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPICCR.6).
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MIN
4t_c(LCO)
MAX
UNIT
ns
Electrical Specifications 127