SM320F28335-EP_12 Datasheet, PDF (34/167 Pages) Texas Instruments – Digital Signal Controller (DSC)

SM320F28335-EP
SPRS581D – JUNE 2009 – REVISED MAY 2012
Table 3-1. Addresses of Flash Sectors
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ADDRESS RANGE
0x30 0000 - 0x30 7FFF
0x30 8000 - 0x30 FFFF
0x31 0000 - 0x31 7FFF
0x31 8000 - 0x31 FFFF
0x32 0000 - 0x32 7FFF
0x32 8000 - 0x32 FFFF
0x33 0000 - 0x33 7FFF
0x33 8000 - 0x33 FF7F
0x33 FF80 - 0x33 FFF5
0x33 FFF6 - 0x33 FFF7
0x33 FFF8 - 0x33 FFFF
PROGRAM AND DATA SPACE
Sector H (32K x 16)
Sector G (32K x 16)
Sector F (32K x 16)
Sector E (32K x 16)
Sector D (32K x 16)
Sector C (32K x 16)
Sector B (32K x 16)
Sector A (32K x 16)
Program to 0x0000 when using the
Code Security Module
Boot-to-Flash Entry Point
(program branch instruction here)
Security Password
(128-Bit) (Do Not Program to all zeros)
NOTE
• When the code-security passwords are programmed, all addresses between 0x33FF80
and 0x33FFF5 cannot be used as program code or data. These locations must be
programmed to 0x0000.
• If the code security feature is not used, addresses 0x33FF80 through 0x33FFEF may be
used for code or data. Addresses 0x33FFF0 – 0x33FFF5 are reserved for data and
should not contain program code. .
Table 3-2 shows how to handle these memory locations.
Table 3-2. Handling Security Code Locations
ADDRESS
0x33FF80 - 0x33FFEF
0x33FFF0 - 0x33FFF5
Code security enabled
Fill with 0x0000
FLASH
Code security disabled
Application code and data
Reserved for data only
Peripheral Frame 1, Peripheral Frame 2, and Peripheral Frame 3 are grouped together to enable these
blocks to be write/read peripheral block protected. The protected mode ensures that all accesses to these
blocks happen as written. Because of the C28x pipeline, a write immediately followed by a read, to
different memory locations, will appear in reverse order on the memory bus of the CPU. This can cause
problems in certain peripheral applications where the user expected the write to occur first (as written).
The C28x CPU supports a block protection mode where a region of memory can be protected so as to
make sure that operations occur as written (the penalty is extra cycles are added to align the operations).
This mode is programmable and by default, it will protect the selected zones.
The wait-states for the various spaces in the memory map area are listed in Table 3-3.
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Functional Overview
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