SM320F28335-EP_12 Datasheet, PDF (122/167 Pages) Texas Instruments – Digital Signal Controller (DSC)

SM320F28335-EP
SPRS581D – JUNE 2009 – REVISED MAY 2012
ADCSOCAO
or
ADCSOCBO
t_w(ADCSOCAL)
Figure 6-17. ADCSOCAO or ADCSOCBO Timing
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6.11 External Interrupt Timing
XNMI, XINT1, XINT2
Address bus
(internal)
t_w(INT)
Figure 6-18. External Interrupt Timing
t_d(INT)
Interrupt Vector
Table 6-28. External Interrupt Timing Requirements⁽¹⁾
t_w(INT) ⁽²⁾
Pulse duration, INT input low/high
TEST CONDITIONS
Synchronous
With qualifier
(1) For an explanation of the input qualifier parameters, see Table 6-12.
(2) This timing is applicable to any GPIO pin configured for ADCSOC functionality.
MIN
1t_c(SCO)
1t_c(SCO) + t_w(IQSW)
Table 6-29. External Interrupt Switching Characteristics⁽¹⁾
MAX
UNIT
cycles
cycles
PARAMETER
t_d(INT)
Delay time, INT low/high to interrupt-vector fetch
(1) For an explanation of the input qualifier parameters, see Table 6-12.
MIN
MAX
t_w(IQSW) + 12t_c(SCO)
UNIT
cycles
122 Electrical Specifications
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