SM320F28335-EP_12 Datasheet, PDF (60/167 Pages) Texas Instruments – Digital Signal Controller (DSC)

SM320F28335-EP
SPRS581D – JUNE 2009 – REVISED MAY 2012
www.ti.com
4.3 Enhanced PWM Modules (ePWM1/2/3/4/5/6)
The F28335 contains up to six enhanced PWM Modules (ePWM). Figure 4-4 shows a block diagram of
multiple ePWM modules. Figure 4-4 shows the signal interconnections with the ePWM.
Table 4-2 shows the complete ePWM register set per module and Table 4-3 shows the remapped register
configuration.
EPWM1SYNCI
EPWM1INT
EPWM1SOC
EPWM1SYNCI
ePWM1 module
EPWM1A
EPWM1B
to eCAP1
and ePWM4
module
(sync in)
EPWM2INT
EPWM1SYNCO
.
EPWM2SYNCI
TZ1 to TZ6
EPWM1SYNCO
EPWM2A
PIE
EPWM2SOC
ePWM2 module
EPWM2B
GPIO
MUX
EPWM2SYNCO
TZ1 to TZ6
EPWMxINT
EPWMxSOC
EPWMxSYNCI
ePWMx module
EPWMxA
EPWMxB
EPWMxSYNCO
TZ1 to TZ6
(A)
ADCSOCxO
ADC
Peripheral Bus
A. ADCSOCxO is sent to the DMA as well when the ePWM registers are remapped to PF3 (through bit 0 of the
MAPCNF register).
B. By default, ePWM/HRPWM registers are mapped to Peripheral Frame 1 (PF1). Table 4-2 shows this configuration. To
re-map the registers to Peripheral Frame 3 (PF3) to enable DMA access, bit 0 (MAPEPWM) of MAPCNF register
(address 0x702E) must be set to 1. Table 4-3 shows the remapped configuration.
Figure 4-4. Multiple PWM Modules
60
Peripherals
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