SM320F28335-EP_12 Datasheet, PDF (143/167 Pages) Texas Instruments – Digital Signal Controller (DSC)

SM320F28335-EP
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SPRS581D – JUNE 2009 – REVISED MAY 2012
6.14.9 XHOLD and XHOLDA Timing
If the HOLD mode bit is set while XHOLD and XHOLDA are both low (external bus accesses granted), the
XHOLDA signal is forced high (at the end of the current cycle) and the external interface is taken out of
high-impedance mode.
On a reset (XRS), the HOLD mode bit is set to 0. If the XHOLD signal is active low on a system reset, the
bus and all signal strobes must be in high-impedance mode, and the XHOLDA signal is also driven active
low.
When HOLD mode is enabled and XHOLDA is active low (external bus grant active), the CPU can still
execute code from internal memory. If an access is made to the external interface, the CPU is stalled until
the XHOLD signal is removed.
An external DMA request, when granted, places the following signals in a high-impedance mode:
XA[19:0]
XZCS0
XD[31:0], XD[15:0] XZCS6
XWE0, XWE1,
XRD
XZCS7
XR/W
All other signals not listed in this group remain in their default or functional operational modes during these
signal events.
Table 6-47. XHOLD/XHOLDA Timing Requirements (XCLKOUT = XTIMCLK) ^{(1) (2)}
MIN
MAX
UNIT
t_d(HL-HiZ)
t_d(HL-HAL)
t_d(HH-HAH)
t_d(HH-BV)
t_d(HL-HAL)
Delay time, XHOLD low to Hi-Z on all address, data, and control
Delay time, XHOLD low to XHOLDA low
Delay time, XHOLD high to XHOLDA high
Delay time, XHOLD high to bus valid
Delay time, XHOLD low to XHOLDA low
4t_{c(XTIM) + 30 ns}
ns
5t_{c(XTIM)+ 30 ns}
ns
3t_{c(XTIM)+ 30 ns}
ns
4t_{c(XTIM)+ 30 ns}
ns
4t_{c(XTIM + 2tc(XCO) + 30 ns}
ns
(1) When a low signal is detected on XHOLD, all pending XINTF accesses will be completed before the bus is placed in a high-impedance
state.
(2) The state of XHOLD is latched on the rising edge of XTIMCLK.
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