SM320F28335-EP_12 Datasheet, PDF (134/167 Pages) Texas Instruments – Digital Signal Controller (DSC)

SM320F28335-EP
SPRS581D – JUNE 2009 – REVISED MAY 2012
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Examples:
XZCSL
XRNWL
Zone chip-select active low
XR/W active low
• Strobes that change at the beginning of the active period will align to the rising edge of XCLKOUT if
the total number of lead XTIMCLK cycles for the access is even. If the number of lead XTIMCLK
cycles is odd, then the alignment will be with respect to the falling edge of XCLKOUT.
Examples:
XRDL
XWEL
XRD active low
XWE1 or XWE0 active low
• Strobes that change at the beginning of the trail period will align to the rising edge of XCLKOUT if the
total number of lead + active XTIMCLK cycles (including hardware waitstates) for the access is even. If
the number of lead + active XTIMCLK cycles (including hardware waitstates) is odd, then the alignment
will be with respect to the falling edge of XCLKOUT.
Examples:
XRDH
XWEH
XRD inactive high
XWE1 or XWE0 inactive high
• Strobes that change at the end of the access will align to the rising edge of XCLKOUT if the total
number of lead + active + trail XTIMCLK cycles (including hardware waitstates) is even. If the number
of lead + active + trail XTIMCLK cycles (including hardware waitstates) is odd, then the alignment will
be with respect to the falling edge of XCLKOUT.
Examples:
XZCSH
XRNWH
Zone chip-select inactive high
XR/W inactive high
6.14.5 External Interface Read Timing
Table 6-37. External Interface Read Timing Requirements
t_a(A)
Access time, read data from address valid
t_a(XRD)
Access time, read data valid from XRD active low
t_su(XD)XRD
Setup time, read data valid before XRD strobe inactive high
t_h(XD)XRD
Hold time, read data valid after XRD inactive high
(1) LR = Lead period, read access. AR = Active period, read access. See Table 6-35.
MIN
MAX UNIT
(LR + AR) –16 ⁽¹⁾
ns
AR –14 ⁽¹⁾
ns
14
ns
0
ns
Table 6-38. External Interface Read Switching Characteristics
PARAMETER
MIN
MAX UNIT
t_{d(XCOH-XZCSL)}
t_{d(XCOHL-XZCSH)}
t_d(XCOH-XA)
t_{d(XCOHL-XRDL)}
t_d(XCOHL-XRDH
t_h(XA)XZCSH
t_h(XA)XRD
Delay time, XCLKOUT high to zone chip-select active low
Delay time, XCLKOUT high/low to zone chip-select inactive high
Delay time, XCLKOUT high to address valid
Delay time, XCLKOUT high/low to XRD active low
Delay time, XCLKOUT high/low to XRD inactive high
Hold time, address valid after zone chip-select inactive high
Hold time, address valid after XRD inactive high
–1
–1.5
(1)
(1)
1 ns
0.5 ns
1.5 ns
0.5 ns
0.5 ns
ns
ns
(1) During inactive cycles, the XINTF address bus always holds the last address put out on the bus except XA0, which remains high. This
includes alignment cycles.
134 Electrical Specifications
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