SM320F28335-EP_12 Datasheet, PDF (156/167 Pages) Texas Instruments – Digital Signal Controller (DSC)

SM320F28335-EP
SPRS581D – JUNE 2009 – REVISED MAY 2012
www.ti.com
Table 6-60. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 1)
NO.
M49
t_su(DRV-CKXH)
M50
t_h(CKXH-DRV)
M51
t_su(FXL-CKXL)
M52
t_c(CKX)
(1) 2P = 1/CLKG
Setup time, DR valid before CLKX high
Hold time, DR valid after CLKX high
Setup time, FSX low before CLKX low
Cycle time, CLKX
MASTER
MIN MAX
30
1
2P ⁽¹⁾
SLAVE
MIN MAX
8P –10
8P –10
8P + 10
16P
UNIT
ns
ns
ns
ns
Table 6-61. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 1)
NO.
M43
M44
M47
t_h(CKXH-FXL)
t_d(FXL-CKXL)
t_{dis(FXH-DXHZ)}
M48 t_d(FXL-DXV)
(1) 2P = 1/CLKG
PARAMETER
Hold time, FSX low after CLKX high
Delay time, FSX low to CLKX low
Disable time, DX high impedance following last data bit from
FSX high
Delay time, FSX low to DX valid
MASTER
MIN
2P ⁽¹⁾
MAX
P
6
SLAVE
MIN MAX
6P + 6
UNIT
ns
ns
ns
6
4P + 6
ns
For all SPI slave modes, CLKX must be a minimum of 8 CLKG cycles. Also, CLKG should be LSPCLK/2
by setting CLKSM = CLKGDV = 1. With maximum LSPCLK speed of 75 MHz, CLKX maximum frequency
will be LSPCLK/16; that is, 4.6875 MHz and P = 13.3 ns.
CLKX
LSB
M51
MSB
M52
M43
M44
FSX
M47
M48
DX
Bit 0
DR
Bit 0
Bit(n-1)
(n-2)
(n-3)
(n-4)
M49
M50
Bit(n-1)
(n-2)
(n-3)
(n-4)
Figure 6-40. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1
Table 6-62. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 1)
NO.
M58
M59
M60
M61
t_su(DRV-CKXL)
t_h(CKXL-DRV)
t_su(FXL-CKXL)
t_c(CKX)
(1) 2P = 1/CLKG
Setup time, DR valid before CLKX low
Hold time, DR valid after CLKX low
Setup time, FSX low before CLKX low
Cycle time, CLKX
MASTER
MIN MAX
30
1
2P ⁽¹⁾
SLAVE
MIN MAX
8P – 10
8P – 10
16P + 10
16P
UNIT
ns
ns
ns
ns
156 Electrical Specifications
Copyright © 2009–2012, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Link(s): SM320F28335-EP