SM320F28335-EP_12 Datasheet, PDF (102/167 Pages) Texas Instruments – Digital Signal Controller (DSC)

SM320F28335-EP
SPRS581D – JUNE 2009 – REVISED MAY 2012
www.ti.com
6.4 Current Consumption
Table 6-1. Current Consumption by Power-Supply Pins at 150-MHz SYSCLKOUT
MODE
TEST CONDITIONS
Operational
(Flash) ⁽⁶⁾
IDLE
STANDBY
HALT ⁽⁸⁾
The following peripheral
clocks are enabled:
• ePWM1/2/3/4/5/6
• eCAP1/2/3/4/5/6
• eQEP1/2
• eCAN-A
• SCI-A/B (FIFO
mode)
• SPI-A (FIFO mode)
• ADC
• I2C
• CPU Timer 0/1/2
All PWM pins are toggled
at 150 kHz.
All I/O pins are left
unconnected. ⁽⁷⁾
Flash is powered down.
XCLKOUT is turned off.
The following peripheral
clocks are enabled:
• eCAN-A
• SCI-A
• SPI-A
• I2C
Flash is powered down.
Peripheral clocks are off.
Flash is powered down.
Peripheral clocks are off.
Input clock is disabled.⁽⁹⁾
I_DD
TYP ⁽⁵⁾
MAX
290 mA 315 mA
100 mA 120 mA
8 mA
15 mA
150 μA
I_DDIO ⁽¹⁾
TYP ⁽⁵⁾
MAX
30 mA 50 mA
60 μA 120 μA
60 μA 120 μA
60 μA 120 μA
I_DD3VFL ⁽²⁾
TYP
MAX
35 mA 40 mA
2 μA
10 μA
2 μA
10 μA
2 μA
10 μA
I_DDA18 ⁽³⁾
TYP ⁽⁵⁾
MAX
30 mA 35 mA
5 μA
60 μA
5 μA
5 μA
60 μA
60 μA
I_DDA33 ⁽⁴⁾
TYP ⁽⁵⁾
MAX
1.5 mA
2 mA
15 μA
20 μA
15 μA
15 μA
20 μA
20 μA
(1) I_DDIO current is dependent on the electrical loading on the I/O pins.
(2) The I_DD3VFL current indicated in this table is the flash read-current and does not include additional current for erase/write operations.
During flash programming, extra current is drawn from the V_DD and V_DD3VFL rails, as indicated in Table 6-66. If the user application
involves on-board flash programming, this extra current must be taken into account while architecting the power-supply stage.
(3) I_DDA18 includes current into V_DD1A18 and V_DD2A18 pins. In order to realize the I_DDA18 currents shown for IDLE, STANDBY, and HALT,
clock to the ADC module must be turned off explicitly by writing to the PCLKCR0 register.
(4) I_DDA33 includes current into V_DDA2 and V_DDAIO pins.
(5) The TYP numbers are applicable over room temperature and nominal voltage. MAX numbers are at 125°C, and MAX voltage (V_DD = 2.0
V; V_DDIO, V_DD3VFL, V_DDA = 3.6 V).
(6) When the identical code is run off SARAM, I_DD would increase as the code operates with zero wait states.
(7) The following is done in a loop:
• Data is continuously transmitted out of the SCI-A, SCI-B, SPI-A, McBSP-A, and eCAN-A ports.
• Multiplication/addition operations are performed.
• Watchdog is reset.
• ADC is performing continuous conversion. Data from ADC is transferred to SARAM through the DMA.
• 32-bit read/write of the XINTF is performed.
• GPIO19 is toggled.
(8) HALT mode I_DD currents will increase with temperature in a non-linear fashion.
(9) If a quartz crystal or ceramic resonator is used as the clock source, the HALT mode shuts down the internal oscillator.
NOTE
The peripheral - I/O multiplexing implemented in the device prevents all available peripherals
from being used at the same time. This is because more than one peripheral function may
share an I/O pin. It is, however, possible to turn on the clocks to all the peripherals at the
same time, although such a configuration is not useful. If this is done, the current drawn by
the device will be more than the numbers specified in the current consumption tables.
102 Electrical Specifications
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