SM320F28335-EP_12 Datasheet, PDF (54/167 Pages) Texas Instruments – Digital Signal Controller (DSC)

SM320F28335-EP
SPRS581D – JUNE 2009 – REVISED MAY 2012
www.ti.com
3.6.1.3 Loss of Input Clock
In PLL-enabled and PLL-bypass mode, if the input clock OSCCLK is removed or absent, the PLL will still
issue a limp-mode clock. The limp-mode clock continues to clock the CPU and peripherals at a typical
frequency of 1-5 MHz. Limp mode is not specified to work from power-up, only after input clocks have
been present initially. In PLL bypass mode, the limp mode clock from the PLL is automatically routed to
the CPU if the input clock is removed or absent.
Normally, when the input clocks are present, the watchdog counter decrements to initiate a watchdog
reset or WDINT interrupt. However, when the external input clock fails, the watchdog counter stops
decrementing (i.e., the watchdog counter does not change with the limp-mode clock). In addition to this,
the device will be reset and the “Missing Clock Status” (MCLKSTS) bit will be set. These conditions could
be used by the application firmware to detect the input clock failure and initiate necessary shut-down
procedure for the system.
NOTE
Applications in which the correct CPU operating frequency is absolutely critical should
implement a mechanism by which the DSC will be held in reset, should the input clocks ever
fail. For example, an R-C circuit may be used to trigger the XRS pin of the DSC, should the
capacitor ever get fully charged. An I/O pin may be used to discharge the capacitor on a
periodic basis to prevent it from getting fully charged. Such a circuit would also help in
detecting failure of the flash memory and the V_DD3VFL rail.
3.6.2 Watchdog Block
The watchdog block on the F28335 is similar to the one used on the 240x and 281x devices. The
watchdog module generates an output pulse, 512 oscillator clocks wide (OSCCLK), whenever the 8-bit
watchdog up counter has reached its maximum value. To prevent this, the user disables the counter or the
software must periodically write a 0x55 + 0xAA sequence into the watchdog key register which will reset
the watchdog counter. Figure 3-11 shows the various functional blocks within the watchdog module.
OSCCLK
WDCR (WDPS[2:0])
WDCR (WDDIS)
Watchdog ^WDCLK
/512
Prescaler
WDCNTR(7:0)
8-Bit
Watchdog
Counter
CLR
Clear Counter
Internal
Pullup
XRS
WDKEY(7:0)
Watchdog
55 + AA
Key Detector
Good Key
Core-reset
WDCR (WDCHK[2:0])
Bad
WDCHK
Key
Generate ^WDRST
Output Pulse _WDINT
(512 OSCCLKs)
SCSR (WDENINT)
WDRST^(A)
101
A. The WDRST signal is driven low for 512 OSCCLK cycles.
Figure 3-11. Watchdog Module
The WDINT signal enables the watchdog to be used as a wakeup from IDLE/STANDBY mode.
54
Functional Overview
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