SM320F28335-EP_12 Datasheet, PDF (132/167 Pages) Texas Instruments – Digital Signal Controller (DSC)

SM320F28335-EP
SPRS581D – JUNE 2009 – REVISED MAY 2012
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These requirements result in the following XTIMING register configuration restrictions :
XRDLEAD
XRDACTIVE
XRDTRAIL
XWRLEAD
XWRACTIVE
XWRTRAIL
≥1
≥2
0
≥1
≥2
0
X2TIMING
0, 1
or
XRDLEAD
≥2
XRDACTIVE
≥1
XRDTRAIL
0
XWRLEAD
≥2
XWRACTIVE
≥1
XWRTRAIL
0
X2TIMING
0, 1
Examples of valid and invalid timing when using asynchronous XREADY:
XRDLEAD XRDACTIVE XRDTRAIL
XWRLEAD XWRACTIVE
Invalid ⁽¹⁾
0
0
0
0
0
Invalid ⁽¹⁾
1
0
0
1
0
Invalid ⁽¹⁾
1
1
0
1
1
Valid
1
1
0
1
1
Valid
1
2
0
1
2
Valid
2
1
0
2
1
(1) No hardware to detect illegal XTIMING configurations
XWRTRAIL
0
0
0
0
0
0
X2TIMING
0, 1
0, 1
0
1
0, 1
0, 1
Unless otherwise specified, all XINTF timing is applicable for the clock configurations shown in Table 6-36.
132 Electrical Specifications
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