SM320F28335-EP_12 Datasheet, PDF (51/167 Pages) Texas Instruments – Digital Signal Controller (DSC)

SM320F28335-EP
www.ti.com
Name
PLLSTS
Reserved
HISPCP
LOSPCP
PCLKCR0
PCLKCR1
LPMCR0
Reserved
PCLKCR3
PLLCR
SCSR
WDCNTR
Reserved
WDKEY
Reserved
WDCR
Reserved
MAPCNF
SPRS581D – JUNE 2009 – REVISED MAY 2012
Table 3-13. PLL, Clocking, Watchdog, and Low-Power Mode Registers
Address
0x00 7011
0x00 7012 - 0x00 7018
0x00 701A
0x00 701B
0x00 701C
0x00 701D
0x00 701E
0x00 701F
0x00 7020
0x00 7021
0x00 7022
0x00 7023
0x00 7024
0x00 7025
0x00 7026 - 0x00 7028
0x00 7029
0x00 702A - 0x00 702D
0x00 702E
Size (x16)
1
7
1
1
1
1
1
1
1
1
1
1
1
1
3
1
6
1
Description
PLL Status Register
Reserved
High-Speed Peripheral Clock Pre-Scaler Register
Low-Speed Peripheral Clock Pre-Scaler Register
Peripheral Clock Control Register 0
Peripheral Clock Control Register 1
Low Power Mode Control Register 0
Low Power Mode Control Register 1
Peripheral Clock Control Register 3
PLL Control Register
System Control and Status Register
Watchdog Counter Register
Reserved
Watchdog Reset Key Register
Reserved
Watchdog Control Register
Reserved
ePWM/HRPWM Re-map Register
3.6.1 OSC and PLL Block
Figure 3-7 shows the OSC and PLL block.
External
Crystal or
Resonator
XCLKIN
(3.3-V clock input
from external
oscillator)
OSCCLK
PLLSTS[OSCOFF]
OSCCLK
0
OSCCLK or
VCOCLK
PLL ^VCOCLK
n _n≠0
/1
/2 ^CLKIN
/4
To
CPU
X1
On-chip
oscillator
X2
PLLSTS[PLLOFF]
PLLSTS[DIVSEL]
4-bit Multiplier PLLCR[DIV]
Figure 3-7. OSC and PLL Block Diagram
The on-chip oscillator circuit enables a crystal/resonator to be attached to the F28335 using the X1 and X2
pins. If the on-chip oscillator is not used, an external oscillator can be used in either one of the following
configurations:
1. A 3.3-V external oscillator can be directly connected to the XCLKIN pin. The X2 pin should be left
unconnected and the X1 pin tied low. The logic-high level in this case should not exceed V_DDIO.
2. A 1.9-V (1.8-V for 100 MHz devices) external oscillator can be directly connected to the X1 pin. The X2
pin should be left unconnected and the XCLKIN pin tied low. The logic-high level in this case should
not exceed V_DD.
The three possible input-clock configurations are shown in Figure 3-8 through Figure 3-10.
Copyright © 2009–2012, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Link(s): SM320F28335-EP
Functional Overview
51