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SM320F28335-EP_12 Datasheet, PDF (35/167 Pages) Texas Instruments – Digital Signal Controller (DSC)
SM320F28335-EP
www.ti.com
SPRS581D – JUNE 2009 – REVISED MAY 2012
Table 3-3. Wait-states
Area
Wait-States (CPU) Wait-States (DMA)(1) Comments
M0 and M1 SARAMs
0-wait
Fixed
Peripheral Frame 0
0-wait (writes)
0-wait (reads)
1-wait (reads)
Peripheral Frame 3
0-wait (writes)
0-wait (writes)
Assumes no conflicts between CPU and DMA.
2-wait (reads)
1-wait (reads)
Peripheral Frame 1
0-wait (writes)
Cycles can be extended by peripheral generated ready.
2-wait (reads)
Consecutive writes to the CAN will experience a 1-cycle
pipeline hit.
Peripheral Frame 2
0-wait (writes)
Fixed. Cycles cannot be extended by the peripheral.
2-wait (reads)
L0 SARAM
L1 SARAM
0-wait data and
program
Assumes no CPU conflicts
L2 SARAM
L3 SARAM
L4 SARAM
0-wait data (read)
0-wait data (write) Assumes no conflicts between CPU and DMA.
L5 SARAM
0-wait data (write)
0-wait data (read)
L6 SARAM
1-wait program (read)
L7 SARAM
1-wait program (write)
XINTF
Programmable
Programmable
Programmed via the XTIMING registers or extendable via
external XREADY signal to meet system timing requirements.
1-wait is minimum wait states allowed on external waveforms
for both reads and writes on XINTF.
0-wait minimum writes
with write buffer
enabled
0-wait minimum writes
with write buffer enabled
0-wait minimum for writes assumes write buffer enabled and
not full.
Assumes no conflicts between CPU and DMA. When DMA and
CPU attempt simultaneous conflict, 1-cycle delay is added for
arbitration.
OTP
Programmable
Programmed via the Flash registers.
1-wait minimum
1-wait is minimum number of wait states allowed. 1-wait-state
operation is possible at a reduced CPU frequency.
FLASH
Programmable
Programmed via the Flash registers.
1-wait Paged min
0-wait minimum for paged access is not allowed
1-wait Random min
Random ≥ Paged
FLASH Password
16-wait fixed
Wait states of password locations are fixed.
Boot-ROM
1-wait
0-wait speed is not possible.
(1) The DMA has a base of 4 cycles/word.
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