SM320F28335-EP_12 Datasheet, PDF (116/167 Pages) Texas Instruments – Digital Signal Controller (DSC)

SM320F28335-EP
SPRS581D – JUNE 2009 – REVISED MAY 2012
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6.9.4 Low-Power Mode Wakeup Timing
Table 6-13 shows the timing requirements, Table 6-14 shows the switching characteristics, and Figure 6-
13 shows the timing diagram for IDLE mode.
Table 6-13. IDLE Mode Timing Requirements⁽¹⁾
t_w(WAKE-INT)
Pulse duration, external wake-up
signal
Without input qualifier
With input qualifier
(1) For an explanation of the input qualifier parameters, see Table 6-12.
MIN
2t_c(SCO)
5t_c(SCO) + t_w(IQSW)
NOM
MAX
UNIT
cycles
Table 6-14. IDLE Mode Switching Characteristics⁽¹⁾
PARAMETER
TEST CONDITIONS
MIN TYP
MAX UNIT
Delay time, external wake signal to
program execution resume ⁽²⁾
t_d(WAKE-IDLE)
Wake-up from Flash
• Flash module in active state
Wake-up from Flash
• Flash module in sleep state
• Wake-up from SARAM
Without input qualifier
With input qualifier
Without input qualifier
With input qualifier
Without input qualifier
With input qualifier
20t_c(SCO)
20t_c(SCO) + t_w(IQSW)
1050t_c(SCO)
1050t_c(SCO) + t_w(IQSW)
20t_c(SCO)
20t_c(SCO) + t_w(IQSW)
cycles
cycles
cycles
(1) For an explanation of the input qualifier parameters, see Table 6-12.
(2) This is the time taken to begin execution of the instruction that immediately follows the IDLE instruction. execution of an ISR (triggered
by the wake up) signal involves additional latency.
Address/Data
(internal)
t_{d(WAKE−IDLE)}
XCLKOUT
WAKE INT^(A)
t_{w(WAKE−INT)}
A. WAKE INT can be any enabled interrupt, WDINT, XNMI, or XRS.
Figure 6-13. IDLE Entry and Exit Timing
Table 6-15. STANDBY Mode Timing Requirements
TEST CONDITIONS
t_w(WAKE-INT)
Pulse duration, external ^{Without input qualification}
wake-up signal
With input qualification⁽¹⁾
(1) QUALSTDBY is a 6-bit field in the LPMCR0 register.
MIN
3t_c(OSCCLK)
(2 + QUALSTDBY) * t_c(OSCCLK)
NOM MAX UNIT
cycles
116 Electrical Specifications
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