LMH1983 Datasheet, PDF (7/55 Pages) National Semiconductor (TI) – Generating 44.1 kHz Based highly integrated programmable audio

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LMH1983
SNLS309I – APRIL 2010 – REVISED DECEMBER 2014
Electrical Characteristics⁽¹⁾ (continued)
Unless otherwise specified, all limits are specified for T_A = 25°C, V_DD = 3.3 V, R_{L_CLK} = 100 Ω (CLKout differential load).
PARAMETER
TEST CONDITIONS
MIN⁽²⁾ TYP⁽³⁾ MAX⁽²⁾ UNIT
Measured at CLKout1, other CLKouts shutdown
27 MHz TIE random Output
Jitter ⁽⁵⁾
Measured at CLKout1, other CLKouts output default
PLL
2.7
ps
2.7
ps
Measured at CLKout2, other CLKouts shutdown
148.5 MHz TIE Random
Output Jitter⁽⁵⁾
Measured at CLKout2, other CLKouts output default
PLL
t_RJ
Measured at CLKout3, other CLKouts shutdown
148.35 MHz TIE Random
Output Jitter ⁽⁵⁾
Measured at CLKout3, other CLKouts output default
PLL
3.0
ps
3.0
ps
3.5
ps
3.5
ps
24.576 MHz TIE Random
Output Jitter⁽⁵⁾
Measured at CLKout4, other CLKouts shutdown
Measured at CLKout4, other CLKouts output default
PLL
3.4
ps
3.4
ps
T_D
Duty cycle
Measured at 50% level of clock amplitude, any
output clock
50%
t_R
Rise time
20% to 80%
15 pF load
400
ps
t_F
Fall time
80% to 20%
15 pF load
400
ps
V_OD
Differential signal output
voltage
100 Ω differential load, CLKout1, CLKout2 or
CLKout3 ⁽⁶⁾
247
350
454 mV
V_OS
Common signal output
voltage
100 Ω differential load, CLKout1, CLKout2 or
CLKout3 ⁽⁶⁾
1.125 1.25 1.375 V
|V_OD|
|Change to V_OD| for
complementary output
states
100 Ω differential load, CLKout1, CLKout2 or
CLKout3 ⁽⁶⁾
50 |mV|
|V_OS|
|Change to V_OS| for
complementary output
states
100 Ω differential load, CLKout1, CLKout2 or
CLKout3 ⁽⁶⁾
50 |mV|
I_OS
Output short circuit current
Differential clock output pins connected to GND for
CLKout1, CLKout2, or CLKout3
24 |mA|
I_OZ
Output shutdown leakage
current
VCXO INPUT (XOin)
Output buffer in shutdown mode, differential clock
output pins connected to V_DD or GND
1
10 |µA|
Maximum relative frequency
f_OFF
offset between VCXO input Assumes H input jitter of ±15 ns
and H input
±150
ppm
V_{XOin_SE}
Single-ended signal input
voltage range
Single-ended input buffer mode
0
V_DD
V
V_{XOin_DIFF}
Differential signal input
voltage range
Differential input buffer mode, V_CM = 1.2 V
247
350
454 mV
DIGITAL HOLDOVER and FREE-RUN SPECIFICATIONS
V_{VCout_RNG} DAC output voltage range Digital Free-run Mode
0.5
V_DD -
0.5V
V
(5) The SD and HD clock output jitter is based on XO input clock with 20 ps peak-to-peak using a time interval error (TIE) jitter
measurement. The typical TIE peak-to-peak jitter was measured on the LMH1983 evaluation bench board using TDSJIT3 jitter analysis
software on a Tektronix DSA71604 oscilloscope and 1 GHz active differential probe. TDSJIT3 Clock TIE Measurement Setup: 10^-12 bit
error rate (BER), >100K samples recorded using multiple acquisitions. Oscilloscope Setup: 20 mV/div vertical scale, 10 µs/div horizontal
scale, and 25 GS/s sampling rate
(6) The differential output swing and common mode voltage may be adjusted via the I²C interface. Testing is done with a value of 0x3E
loaded into Register 0x3A.
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