LMH1983 Datasheet, PDF (17/55 Pages) National Semiconductor (TI) – Generating 44.1 kHz Based highly integrated programmable audio

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LMH1983
SNLS309I – APRIL 2010 – REVISED DECEMBER 2014
Feature Description (continued)
Aside from the time required for the PLL to lock, there is a circuit that determines how to set the NO_LOCK
output pin. The LMH1983 PLL operates by adjusting the voltage that is applied to the VCXO control pin to lock
the VCXO to a harmonic of the incoming reference. When the device is not locked, the PLL pulls the VCXO
control voltage to one extreme of its range to slew the voltage into lock. Once the phase differences between the
VCXO and the reference are small, the device begins to nudge the control voltage back and forth to maintain the
phase difference. An adjustment might be necessary either due to VCXO drift or due to jitter on the reference. To
determine the status of NO_LOCK, the LMH1983 establishes a window to view the amount of adjustment that is
required over a period of time. Two parameters are set via register control to determine NO_LOCK status.
LockStepSize (Register 0x2D) sets the amount of time in which to observe the signal, and Loss of Lock
Threshold (Register 0x1C) sets the amount of variation in the control voltage that can be seen over this time
frame while still considering the device to be locked.
To minimize the amount of time necessary to assert lock, load LockStepSize (Register 0x2D) with a value of
0x01 and the Loss of Lock Threshold (Register 0x1C) with a value of 0x1F. The effect of this change can be
seen in Figure 13:
reference
(input)
NOREF
(output)
NOLOCK
(output)
LOCK ~ 4.4s
reference
(input)
NOREF
(output)
NOLOCK
(output)
LOCK ~ 760 ms
Figure 13. Faster NO_LOCK Reaction Mode Timing
8.3.8 LOR Determination
When the PLL is not locked, there is an internal counter that counts the number of 27 MHz clock pulses between
consecutive HSync pulses divide-by-two. This counter saturates at 0x7FFF (or 32767 decimal). Once this
counter saturates, LOR is declared. Given this is a divide-by-two counter, the time to declare LOR is: (2 x 32767)
/ (27E6) = 2.4 ms. On the other hand, when the PLL is locked and there are missing HSync pulses, LOR is set
when the internal counter is greater than the following: (Number of 27 MHz clocks in one Hsync pulse + 3) x
(LOR_THRES + 1).
8.3.9 Output Driver Adjustments
The LVDS output drivers can be adjusted via the I²C interface to change the differential output voltage swing, the
common mode voltage, and the amount of pre-emphasis applied to the LVDS output:
• Register 0x3A, Bit 7 turns on the pre-emphasis, which may be used to extend the reach between the
LMH1983 and the load. It is recommended that the trace length is kept short, as longer traces have more
opportunity to couple with hostile signals and degrade jitter performance.
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