LMH1983 Datasheet, PDF (26/55 Pages) National Semiconductor (TI) – Generating 44.1 kHz Based highly integrated programmable audio

LMH1983
SNLS309I – APRIL 2010 – REVISED DECEMBER 2014
8.6 Register Map
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The following table provides details on the device's configuration registers. Default value for fields that are seven
bits or less are expressed in binary, and default values for fields that are 8 bits (Byte) are expressed in hex. Do
not write to Reserved (RSVD) fields.
ADD NAME
0x00
Device Status
— Input Reference
0x01 Device Status
0x02
PLL Lock and Output
Alignment Status
0x03 Revision ID
0x04 Reserved
0x05 Device Control
Table 3. LMH1983 Register Map
BITS FIELD
7
INTERLACED
6
ANALOG_REF
5
INPUT_POLARITY
4
HSYNC_STATUS
3
H_ONLY
2
LOR_STATUS
1
LOST_HSYNC
0
Reserved
7
Lock_Status
6
Align_Status
5
Wrong_Format
4
Holdover
3:0 RSVD
7:4 Lock_Detect
3:0 Align_Detect
7:0
7:0 RSVD
7
Soft_Reset
6
Powerdown
5
EN_AFD
4:3 PLL1_Mode
2
LOR Mode
1
Force_148
0
GOE
R/W DEFAULT
DESCRIPTION
R
—
Indicates if the input reference format is an interlaced format
This bit is set depending on if the sync detection circuit had
R
—
determined if the reference is an analog or digital derived
signal
R
—
Returns the value of the input polarity determined by the sync
detector for HSYNC — 0 indicates an active low sync
R
—
This bit is set if the Hsync During Vsync detector will set
NO_H_DURING_V on the next rising edge of VSYNC
R
—
This is set by the Interlaced detector
R
—
Returns the inverse of the NO_REF output pin state
R
—
Set if HSYNC_MISSING is high wile no_h_during_v is low.
Remains set until read, then self-clears
R
0
Reserved — always returns '0'
R
1
Returns lock status for all unmasked and enabled PLLs
R
0
Returns the Align Status for all enabled TOFs
R
1
Returns the value of the Wrong_Format bit.
R
0
Returns the value of the PLL Holdover Bit
0000 Reserved
[7] indicates the lock status of PLL4.
[6] indicates the lock status of PLL3.
R
—
[5] indicates the lock status of PLL2.
[4] indicates the lock status of PLL1.
0 = PLL Not Locked
1 = PLL Locked
[3] indicates the lock status of TOF4.
[2] indicates the lock status of TOF3.
R
—
[1] indicates the lock status of TOF2.
[0] indicates the lock status of TOF1.
0 = TOF Alignment not detected
1 = TOF alignment detected
R
0xC0 Returns device revision code
0x00
Reserved
R/W
0
Writing a ‘1’ will reset all registers to their default values. This
bit is self-clearing and always returns ‘0’ when read.
R/W
0
Controls the power down function.
Enables Auto Format Detection (AFD).
R/W
1
0 = Auto Format Detect disabled
1 = Auto Format Detect enabled
Sets PLL1 operating mode:
00 = Force Free-run
R/W
01
01 = Genlock
10 = Force Holdover
11 = Reserved
Sets default mode of operation on Loss of Reference (LOR)
R/W
0
condition:
0 = Holdover on LOR
1 = Free-run on LOR
When this bit is set, it forces the PLL2 and PLL3 clock rates to
148.xx MHz regardless of chosen output format. Otherwise,
R/W
1
the native clock rate of the chosen output format will be used.
0 = Uses the native clock rates
1 = Forces PLL2 = 148.5 MHz and PLL3 = 148.35 MHz clock
rate
Global Output Enable
R/W
1
0 = Disables all CLKout and Fout output buffers (Hi-Z)
1 = Enable active outputs
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