LMH1983 Datasheet, PDF (12/55 Pages) National Semiconductor (TI) – Generating 44.1 kHz Based highly integrated programmable audio

LMH1983
SNLS309I – APRIL 2010 – REVISED DECEMBER 2014
8.2 Functional Block Diagram
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= Device pins
External Loop Filter and VCXO
27 MHz
VCXO
VC_LPF
XOin+
10-Bit SAR
ADC
DAC
Vc(Freerun)
Vc(Genlock)
Hin
Ref
Input Format
Vin
and Polarity
Detection
PLL1
Genlock PLL
Fin
Fbk
ADDR
Device
Control and
Registers
NO_REF
NO_ALIGN
NO_LOCK
V_DD/2
XOin-
27.0
(13.5)
MHz
TOF1
PLL2
3G(HD)
Video Clock
PLL3
3G(HD)/1.001
Video Clock
In1
148.5
(74.25)
Out2
MHz
In2 _3x2
Video Clock
Crosspoint
148.35,
(74.176)
MHz
Out3
In3
CLKout1+
CLKout1-
Fout1
CLKout2+
CLKout2-
CLKout3+
CLKout3-
SDA
SCL
I²C Interface
I²C Address Options: 0x65h-67h
MUX
PLL4
Audio Clock
98.304 MHz,
others*
AFS/Word
* Audio Clock PLL supports 98.304/2^X MHz, where X=0-15
27 MHz_Osc
Fout2
Fout3
CLKout4+
CLKout4-
Fout4
(Osc In)
8.3 Feature Description
The following subsections provide information about the various control mechanisms and features that are
fundamental to the LMH1983 clock generator.
8.3.1 Control of PLL1
PLL1 generates a 27 MHz reference that is used as the primary frequency reference for all of the other PLLs in
the device. PLL1 has a dual loop architecture with the primary loop locking the external 27 MHz VCXO to a
harmonic of the H_IN signal. In addition to this loop, there is a secondary loop that may be used in genlock
operations. This second loop compares the phase of the TOF1 output signal from the LMH1983 to the F_IN signal.
In order to bring the frame alignment of the output signals into sync with the input reference, the second loop
may override the primary loop. Detailed information about controlling this functionality is described in TOF1
Alignment.
To illustrate the dual loop architecture of PLL1, refer to the PLL1 block diagram in Figure 9. The primary loop
takes the reference applied to the H_IN input and divides that by R (stored in Registers 0x29 and 0x2A). The
dividend is then compared in phase and frequency to the output of the external 27 MHz VCXO divided by N
(stored in Registers 0x2B and 0x2C). The PFD (phase frequency detector) then generates output pulses that are
integrated via an external loop filter that drives the control voltage of the external VCXO.
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