LMH1983 Datasheet, PDF (34/55 Pages) National Semiconductor (TI) – Generating 44.1 kHz Based highly integrated programmable audio

LMH1983
SNLS309I – APRIL 2010 – REVISED DECEMBER 2014
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REGISTER 0x09 [3:0]
0000 (default)
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Table 4. Crosspoint Output Selection Table
PLL2_DISABLE ⁽¹⁾
PLL3_DISABLE ⁽¹⁾
OUT2 SOURCE
0
0
PLL2
1
1
PLL1
0
1
PLL2
1
0
PLL3
0
0
PLL3
1
0
PLL1
0
1
PLL2
0
1
PLL1
1
0
PLL3
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
OUT3 SOURCE
PLL3
PLL1
PLL2
PLL3
PLL2
PLL3
PLL1
PLL2
PLL1
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
(1) PLL2_Disable and PLL3_Disable can be forced via register writes to the PLLx_DISABLE registers independently of the status of the
Crosspoint Mode bits.
Table 5. Vsync Codes
Vsync CODE
NUMBER (BINARY)⁽¹⁾
0 (0000)
1 (0001)
2 (0010)
3 (0011)
4 (0100)
5 (0101)
6 (0110)
7 (0111)
FRAME RATE (Hz)
23.98 Hz
24 Hz
25 Hz
29.97 Hz
30 Hz
50 Hz
59.94 Hz
60 Hz
(1) Vsync codes are used by Registers 0x21 (Output Frame Lookup –
Input Vsync Code), 0x22 (Output Frame Lookup – PLL2 Vsync
Code), and 0x23 (Output Frame Lookup – PLL3 Vsync Code).
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