LMH1983 Datasheet, PDF (33/55 Pages) National Semiconductor (TI) – Generating 44.1 kHz Based highly integrated programmable audio

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LMH1983
SNLS309I – APRIL 2010 – REVISED DECEMBER 2014
Register Map (continued)
ADD NAME
0x47
TOF3 Advanced Control
Frame Reset MSB
0x48
0x49
TOF3 Advanced Control
Frame Reset LSB
TOF4 Advanced Control
AFS
0x4A
TOF4 Advanced Control
ACLK
0x4B
to
0x50
0x51
Reserved
User Auto Format
27M High Value MSB
0x52
User Auto Format
27M High Value LSB
0x53
User Auto Format
27M Low Value MSB
0x54
User Auto Format
27M Low Value LSB
0x55
User Auto Format
R divider MSB
0x56
User Auto Format
R Divider LSB
0x57
User Auto Format
N Divider MSB
0x58
0x59
User Auto Format
N Divider LSB
User Auto Format
Charge Pump Current
0x5A
User Auto Format
LPF MSB
0x5B
0x5C
User Auto Format
LPF LSB
User Auto Format
AFS
0x5D
User Auto Format
Misc
Table 3. LMH1983 Register Map (continued)
BITS
7:5
4:0
FIELD
RSVD
TOF3_RST_MSB
7:0 TOF3_RST_LSB
R/W DEFAULT
DESCRIPTION
000
Reserved
R
00000
Automatically loaded based on formats selected.
R
0x01
7:0 TOF4_AFS
7:4 RSVD
3:0 TOF4_ACLK
R/W
0x05
See Detailed Description section for details. See also PLL4
Block Diagram.
0000 Reserved
R/W
1011
See Detailed Description section for details. See also PLL4
Block Diagram.
7:0 RSVD
0x00
Reserved
7:0 USR_27M_High_MSB R/W
7:0 USR_27M_High_LSB
R/W
7:0 USR_27M_Low_MSB
R/W
7:0 USR_27M_Low_LSB
R/W
7:2 RSVD
1:0 USR_DIV_R1_MSB
R/W
0x00
0x00
0x00
0x00
000000
00
User format detect is determined by looking at the frequency
of the Hsync input. This frequency is measured by counting
the number of 27 MHz clock cycles that occur in 20 Hsync
periods. This 16 bit register lists the maximum number of 27
MHz clock cycles in 20 Hsync periods that could be
considered to meet the criteria for the User Format
User format detect is determined by looking at the frequency
of the Hysnc input. This frequency is measured by counting
the number of 27 MHz clock cycles that occur in 20 Hsync
periods. This 16 bit register lists the minimum number of 27
MHz clock cycles in 20 Hsync periods that could be
considered to meet the criteria for the User Format
Reserved
See Detailed Description section for details.
7:0 USR_DIV_R1_LSB
R/W
0x00
See Detailed Description section for details.
7
RSVD
6:0 USR_DIV_N1_MSB
0
Reserved
R/W 0000000 See Detailed Description section for details.
7:0 USR_DIV_N1_LSB
R/W
0x00
See Detailed Description section for details.
7:0 USR_ICP
R/W
7:5 RSVD
4:0 USR_TOF_LPF_MSB R/W
7:0 USR_TOF_LPF_MSB R/W
0x00
000
00000
0x00
See Detailed Description section for details.
Reserved
See Detailed Description section for details.
See Detailed Description section for details.
7:0 USR_TOF4
R/W
7
EN_USERMODE
R/W
6:5 RSVD
4
USR_IINTERLACED
R/W
3:0 USR_IN_VS_CODE
R/W
0x00
0
00
0
0000
See Detailed Description section for details.
Enables the Auto Format Detection User Mode.
0 = disabled
1 = enabled
Reserved
Sets the INTERLACED value to output from LUT1 if the
INPUT_FORMAT register is set to the user code. This bit also
specifies the value that the Auto Format Detection must see
on the interlaced signal to detect the user defined mode.
Sets the INPUT_VS_CODE value to output from LUT1 if the
INPUT_FORMAT registers is set to the user code.
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